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| dat a sheet r - in32m3 series r18ds0008ej0204 lsi for industrial ethernet dec 25, 2014 r18ds0008ej0204 page 1 of 100 dec 25, 2014 1. overview 1.1 introduction ethernet communication continues to spread rapidly in the field of industrial automation as manufacturers seek to improve the capability, efficiency, and flexibility of their organizations. modern industrial ethernet applications requ ire high - speed real - time response, low power consumption, and high performance. these requirements are not necessarily met by traditional methods such as hard - wired ethernet processors or dedicated high - speed cpus. renesas' r - in32m3 series of large - scale integrated circuits (lsi) are specifically tailored to meet the demands of industrial ethernet applications. key features include: ? high - speed, real - time, deterministic, low - latency, low - jitter response for real - time applications ? low power consumption ? integrated arm cortex - m3 core for flexibility ? integrated r eal - time os accelerator with support for itron version 4.0 ? integrated gigabit ethernet mac (r - in32m3 - cl only) ? integrated 10/100mbps etherphy (r - in32m3 - ec only) ? dedicated, dma controller and buffer for the network processor ? high performance with low cpu usage by offloading functions to r eal - time os accelerator ? multiple timers, serial interfaces, general purpose i/o (gpio), external memory interfaces 1.2 product lineup renesas ? s r - in32m3 series includes the following two d evices: table 1 . 1 r - in32m 3 product lineup p roduct name feature r - in32m3 - ec r - in32m3 with built - in ether cat tm slave controller r - in32m3 - cl r - in32m3 with built - in cc - link ie field tm (intelligent device station)
r - in32m3 series data sheet 1 . overview r18ds0008ej0204 page 2 of 100 dec 25, 2014 1.3 overview table1.2 overview of r - in32m3 (1/2) product item r - in32m3 cpu core s arm cortex - m3 32 - bit risc cpu + real - time os accelerator (hardware real - time os, hw - rtos) o perating frequency 100 mhz i nstruction set thumb ? - 2 instruction armv7 - m a rchitecture i nstruction ram 768k b yte ( ram w/ ecc ) data ram 512kbyte ( ram w/ ecc ) buffer ram 64kbyte ( ram w/ ecc ) internal system bus - 32- bit system bus at 100mhz - 128 - bit communication bus at 100mhz dma - 4 channel s + 1 chann el (for r eal - time port) - supports software and /or various interrupt - triggered dma b oot options - serial flash rom boot - e xternal memory boot - external mp u boot external memory support - 16- bit or 32- bit b us interface - page rom / rom / sram interface - s ynchronous burst memory interface - four chip select s for external sram - 256mbyte (max) e x ternal memory space - programmable wait function external mp u interface - 16- bit or 32- bit bus interface - general - purpose interface for static memory - address space:2mbyte (instruction ram, data ram, register area) serial flash rom memory controller - support serial interface compatible with spi of the companies - support direct boot from serial memory device - support fast read, fast read dual output, fast r ead dual i/o mode - direct layout in memory space interrupt support - 29 e xternal interrupt ports internal peripheral s i/o ports - 96 cmos i/o ports (max) system t imer s - hardware rtos interal timer - cpu internal timer - 4 channel s timer arra y - 32- bit counter & 32- bit data register - counter by external signal watchdog timer - 1 channel - software - trigger ed start mode - watchdog error response options: - generate non - maskable interrupt (nmi) - generate reset r - in32m3 series data sheet 1 . overview r18ds0008ej0204 page 3 of 100 dec 25, 2014 table1.2 overview of r - in32m3 (2/2) product item r - in32m3 internal peripheral s (cont.) a synchronous serial interf ace - 2 channel s - full duplex - fifo s: 10 - bit x 16 receive and 8 - bit x 16 transmit - support output of receive error s and status - c haracter length : 7 or 8 - bit - parity bit options : odd , even, 0 - , no ne - t ransmit stop bit s : 1 or 2 - bit i2c serial interface - 2 channel s - operation mode s : normal or high - speed - transfer mode s : single - transfer mode, or continuous - transfer mode - transmission data length: 8 - bit can controller - 2 channel s - c onforming to iso11898 - s upport to transfer and receive normal frame and expand frame - transmission speed: 1mbps (max) clock synchronized serial interface - 2 channel s - synchronized serial data transmission by three - wire system - selectable master mode or slave mode - built - in baud - rate generator - transmission data length : 7bit - 16bit cc- link - intelligent device station note3 r - in32m3 series data sheet 1 . overview r18ds0008ej0204 page 4 of 100 dec 25, 2014 1.4 i nternal block diagram 1.4.1 r - in32m3 - ec block diagram r -i n 3 2 m3 -ec c o r t e x - m 3 c p u d e b u g n v i c h a r d w a r e r e a l- t im e o s o s d m a c m e m c s e le c t o r s e r ia l f la s h r o m m e m c d a t a r a m 5 1 2 k b ( e c c ) i n s t r u c t io n r a m 7 6 8 k b ( e c c ) e x t _ m ic o n i n t e r f a c e a h b _ a p b b r id g e h a r d w a r e f u n c t io n c o n t r o l h e a d e r e n d e c e t h e r s w i t c h e t h e r c a t b u f f e r a llo c a t o r 1 2 8 b it h a r d w a r e f u n c t io n b u s 1 2 8 b it c o m m u n ic a t io n b u s a p b p h y p h y m a c _ t o p d m a c _ r t p o r t m a c _ d m a g ig a b it e t h e r b u f f e r i d i n t _ d m a timer array uart 2 ch i 2 c 2 ch can 2 ch csi 2 ch wdt b r id g e m u x b r id g e c c - l in k r e a l- t im e g p i o g p i o m u x b u f f e r r a m 6 4 k b ( e c c ) a h b 2 d m a s s s s s s s s s s s m u x s s s s s m u x s s s m u x m u x s s s s s s s m u x s s s m u x s s m u x s s s s m u x m m s m s s m m m m s m m s m m s s c p u s y s t e m c p u d - c o d e c p u i - c o d e d m a c d m a c _ r t p o r t h o s t _ c p u c p u s y s t e m c p u d - c o d e c p u i - c o d e d m a c d m a c _ r t p o r t h o s t _ c p u r - in32m3 series data sheet 1 . overview r18ds0008ej0204 page 5 of 100 dec 25, 2014 1.4.2 r - in32m3 - cl block diagram r - i n 3 2 m 3 - c l c o r t e x - m 3 c p u d e b u g n v i c h a r d w a r e r e a l - t i m e o s o s d m a c m e m c s e l e c t o r s e r i a l f l a s h r o m m e m c d a t a r a m 5 1 2 k b ( e c c ) i n s t r u c t i o n r a m 7 6 8 k b ( e c c ) e x t _ m i c o n i n t e r f a c e a h b _ a p b b r i d g e h a r d w a r e f u n c t i o n c o n t r o l h e a d e r e n d e c e t h e r s w i t c h c c - l i n k i e f i e l d n e t w o r k b u f f e r a l l o c a t o r 1 2 8 b i t h a r d w a r e f u n c t i o n b u s 1 2 8 b i t c o m m u n i c a t i o n b u s a p b p h y p h y m a c _ t o p d m a c _ r t p o r t m a c _ d m a g i g a b i t e t h e r b u f f e r i d i n t _ d m a timer array uart 2 ch i 2 c 2 ch can 2 ch csi 2 ch wdt b r i d g e m u x b r i d g e c c - l i n k r e a l - t i m e g p i o g p i o m u x b u f f e r r a m 6 4 k b ( e c c ) a h b 2 d m a s s s s s s s s s s s m u x s s s s s m u x s s s m u x m u x s s s s s s s m u x s s s m u x s s m u x s s s s m u x m m s m s s m m m m s m m s m m s s c p u s y s t e m c p u d - c o d e c p u i - c o d e d m a c d m a c _ r t p o r t h o s t _ c p u c p u s y s t e m c p u d - c o d e c p u i - c o d e d m a c d m a c _ r t p o r t h o s t _ c p u r - in32m3 series data sheet 1 . overview r18ds0008ej0204 page 6 of 100 dec 25, 2014 1.5 memory m aps synchronous burst access memc control registers area 8 kbyte reserved reserved cc - link master slave bridge control registers 1 k byte reserved real - time port 1 k byte gpio 1 k byte dma controller rtport control registers area 1 k byte dma controller control registers area 1 k byte serial flash rom memory controller control registers area 1 k byte asynchronous sram memc control registers area 1 k byte reserved qint bufid 4 k byte giga bit ether 4 k byte hw - rtos 64k byte reserved buffer memory area 128m byte external memory area 256 mbyte data ram area 512 k byte reserved bitband alias area 16 mbyte reserved apb peripheral registers area 512k byte ahb peripheral registers area 192k byte reserved ether cat area 12 kbyte reserved cc - link master memory area 8 k byte cc - link master i / o area 4 k byte cc - link slave area 4 k byte serial flash rom area 32m byte instruction ram area 768k byte reserved instruction ram mirror area 768 kbyte b itband a lias area 32m byte reserved reserved cortex - m 3 system level area 512 mbyte 040 c 0000 h 400 b 0000 h 400 e 30 00 h ffff ffffh e 000 0000 h 44 00 0000 h 400 f c 000 h 4200 0000 h 040 b ffffh 0400 0000 h 000 b ffffh 03 ff ffffh 0200 0000 h 0000 0000 h system area icode , dcode area dfff ffff h 43 ff ffff h 400 f bfffh 400 f b 000 h 400 f afffh 400 f a 000 h 400 f 9 fffh 400 f 8000 h 400 e 2 f ffh 400 e 0000 h 400 a ffffh 4008 0000 h 4007 ffffh 4000 0000 h 2200 0000 h 22 ff ffffh 200 8 0000 h 2000 0000 h 2007 ffffh 1000 0000 h 1 fff ffffh 0 fff ffffh 0800 0000 h 000 c 0000 h 400 8 0 000 h 4009 0000 h 4009 1000 h 4009 2 000 h 400 a 2000 h 400 a 2400 h 400 a 2800 h 400 a 2 c 00 h 400 a 3000 h 400 a 3400 h 400 a 4400 h 400 a 4800 h 400 a ffffh 400 a 80 00 h figure 1 . 1 memory map (all) (r - in32m3 - ec) < r> r - in32m3 series data sheet 1 . overview r18ds0008ej0204 page 7 of 100 dec 25, 2014 synchronous burst access memc control registers area ( 8 kbyte ) reserved reserved cc - link ( master / slave ) bridge control registers ( 1 k byte ) cc - link ie field network bridge control registers ( 1 k byte ) reserved real - t ime port ( 1 k byte ) gpio ( 1 k byte ) dma controller rtport control registers area ( 1 k byte ) dma controller control registers area ( 1 k byte ) serial flash rom memory contoroller control registers area ( 1 k byte ) asynchronous sram memc control registers area ( 1 k byte ) reserved qint bufid ( 4 k byte ) giga bit ether ( 4 k byte ) hw - rtos ( 64 k byte ) reserved buffer memory area ( 128 m byte ) external memory area ( 256 mbyte ) data ram area ( 512 k byte ) reserved bitband alias area ( 16 mbyte ) reserved apb peripheral registers area ( 512 k byte ) ahb peripheral registers area ( 192 k byte ) reserved cc - link master memory area ( 8 k byte ) cc - link master i / o area ( 4 k byte ) cc - link slave area ( 4 k byte ) serial flash rom area ( 32 m byte ) instruction ram area ( 768 k byte ) reserved instruction ram mirror area ( 768 kbyte ) reserved cc - link ie field network area ( 256 k byte ) bitband alias area ( 32 m byte ) reserved reserved cortex - m 3 system level area ( 512 mbyte ) 040 c 0000 h 400 b 0000 h ffff ffffh e 000 0000 h 44 00 0000 h 4014 0000 h 4013 ffffh 4010 0000 h 400 f c 000 h 4200 0000 h 040 b ffffh 0400 0000 h 000 b ffffh 03 ff ffffh 0200 0000 h 0000 0000 h system area icode , dcode area dfff ffff h 43 ff ffff h 400 f bfffh 400 f b 000 h 400 f afffh 400 f a 000 h 400 f 9 fffh 400 f 8000 h 400 f 7 fffh 400 a ffffh 4008 0000 h 4007 ffffh 4000 0000 h 2200 0000 h 22 ff ffffh 200 8 0000 h 2000 0000 h 2007 ffffh 1000 0000 h 1 fff ffffh 0 fff ffffh 0800 0000 h 000 c 0000 h 400 8 0 000 h 4009 0000 h 4009 1000 h 4009 2 000 h 400 a 2000 h 400 a 2400 h 400 a 2800 h 400 a 2 c 00 h 400 a 3000 h 400 a 3400 h 400 a 4000 h 400 a 4400 h 400 a 4800 h 400 a ffffh 400 a 80 00 h figure 1 . 2 memory map (all) (r - in32m3 - cl) r - in32m3 series data sheet 1 . overview r18ds0008ej0204 page 8 of 100 dec 25, 2014 watchdog timer 16 byte reserved reserved uart 1 128 byte csi 1 256 byte reserved ether switch control register area 64 k byte reserved system register area 64 k byte uart 0 128 byte reserved iic 1 ( 64 byte ) can 1 area 128 k byte can 0 area 128 k byte iic 0 ( 64 byte ) reserved timer ta u j 256 byte csi 0 256 byte reserved apb peripheral registers area 512 k byte ahb peripheral registers area 192 k byte reserved 400 b 0000 h 400 a ffffh 4008 0000 h 4007 ffffh 4000 0000 h 4000 0000 h 4000 0100 h 4000 0200 h 4000 0500 h 4002 0000 h 4004 0000 h 4000 0300 h 4001 0000 h 4007 0000 h 4007 ffffh 4000 0400 h 4000 0600 h 4000 0700 h figure 1 . 3 memory map (apb peripheral registers area ; common to r - in32m3 - ec/cl) r - in32m3 series data sheet 1 . overview r18ds0008ej0204 page 9 of 100 dec 25, 2014 buffer memory area ( 128 m byte ) external memory area ( 256 mbyte ) data ram area ( 512 k byte ) csz 2 area ( 64 m byte ) csz 1 area ( 64 m byte ) csz 3 area ( 64 m byte ) csz 0 area ( 64 m byte ) reserved reserved 1000 0000 h 1400 0000 h 1 c 00 0000 h 1800 0000 h 200 8 0000 h 2000 0000 h 2007 ffffh 1000 0000 h 1 fff ffffh 0 fff ffffh 0800 0000 h 1 fff ffffh 1 bff ffffh 17 ff ffffh 13 ff ffffh figure 1 . 4 memory map (external memory area ; common to r - in32m3 - ec/cl) reserved reserved cc - link master memory area receive buffer ( 3328 byte ) reserved cc - link master memory area pat 1 ( 256 byte ) cc - link master memory area transmit buffer 2 ( 924 byte ) reserved cc - link master memory area pat 0 ( 256 byte ) reserved cc - link master i / o area ( 4 k byte ) cc - link slave area ( 4 k byte ) cc - link master memory area ( 8 k byte ) cc - link master i / o area ( 4 kbyte ) cc - link master memory area transmit buffer 1 ( 924 byte ) reserved reserved 400 f bfffh 400 f b 000 h 400 f afffh 400 f a 000 h 400 f 9 fffh 400 f 8000 h 400 f 8000 h 400 f 839 fh 400 f 8400 h 400 f 84 ffh 400 f 8800 h 400 f 8 b 9 fh reserved 400 f 8 c 00 h 400 f 9000 h 400 f 9 cffh 400 f a 100 h 400 f a 37 fh 400 f afffh f igure 1 . 5 memory map (cc - link master area ; common to r - in32m3 - ec/cl) caution 1. cc - link master shows the function block of intelligent device station. 2. cc - link slave shows the function block of the remote d evice station. r - in32m3 series data sheet 1 . overview r18ds0008ej0204 page 10 of 100 dec 25, 2014 reserved reserved reserved system registers area 64 k byte ether cat area 8 . 125 kbyte hostif registers area 256 byte data ram area 512 k byte a h b peripheral area upper 52 k byte reserved cc - link master momory area 8 k byte cc - link master i / o area 4 k byte cc - link slave area 4 k byte instruction ram area 768 k byte reserved reserved system registers area 64 k byte mcu area 2 mbyte data ram area 512 k byte a h b peripheral area upper 52 k byte ether cat area 8 . 125 kbyte reserved cc - link master memory area 8 k byte cc - link master i / o area 4 k byte cc - link slave area 4 k byte instruction ram area 768 k byte reserved reserved 400 e 30 00 h 400 f c 000 h 000 b ffffh 000 d 2 fffh 0000 0000 h 400 f bfffh 400 f b 000 h 400 f afffh 400 f a 000 h 400 f 9 fffh 400 f 8000 h 400 e 2 f ffh 400 e 0000 h 400 a ffffh 400 a 3000 h 2000 0000 h 2007 ffffh 000 c 0000 h 4001 ffffh 4001 0000 h 4 gbyte internal ahb area 400 e 0 f 8 0 h figure 1 . 6 external mp u interface area (r - in32m3 - ec) < r> r - in32m3 series data sheet 1 . overview r18ds0008ej0204 page 11 of 100 dec 25, 2014 reserved cc - link ie field network area ( 256 k byte ) system registers area ( 64 k byte ) hostif registers area ( 256 byte ) data ram area ( 512 k byte ) a h b peripheral area ( upper 52 k byte ) reserved cc - link master momory area ( 8 k byte ) cc - link master i / o area ( 4 k byte ) cc - link slave area ( 4 k byte ) instruction ram area ( 768 k byte ) reserved reserved cc - link ie field network area ( 256 k byte ) system registers area ( 64 k byte ) 17 ffffh 14 0000 h 13 ffffh 10 0000 h 0 f c 000 h 0 d 0000 h 0 b ffffh 00 0000 h 0 d ffffh 0 f bfffh 0 f b 000 h 0 f afffh 0 f a 000 h 0 f 9 fffh 0 f 8000 h 0 c ffffh 0 c 3000 h 18 0000 h 1 f ffffh 0 c 0000 h 0 e 0000 h 0 f ffffh 0 f ff 00 h mcu area 2 mbyte data ram area ( 512 k byte ) a h b peripheral area ( upper 52 k byte ) reserved cc - link master memory area ( 8 k byte ) cc - link master i / o area ( 4 k byte ) cc - link slave area ( 4 k byte )) instruction ram area ( 768 k byte ) reserved reserved 400 f c 000 h 000 b ffffh 000 d 2 fffh 0000 0000 h 400 f bfffh 400 f b 000 h 400 f afffh 400 f a 000 h 400 f 9 fffh 400 f 8000 h 400 f 7 fffh 400 a ffffh 400 a 3000 h 2000 0000 h 2007 ffffh 000 c 0000 h 4001 ffffh 4001 0000 h 4 gbyte internal ahb area 13 ffffh 10 0000 h internal sram area 2 mbyte 00 0000 h 1 f ffffh 0 f 7 fff h ffff ffffh 400 e 0000 h figure 1 . 7 external mp u interf ace area (r - in32m3 - cl) r - in32m3 series data sheet 2 . pin information r18ds0008ej0204 page 12 of 100 dec 25, 2014 2. pin information 2.1 pin placement (r - in32m3 - ec top view) 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 v gnd p53 trace clk trace data0 resetz boot1 ccm_ clk80m vdd33 p 1 _ rd_n p 1 _ sd_n vdd33 p 1 _td_ out_n p 1 _fx_ en_out p12 p31 p32 p35 gnd v u p56 p55 p54 trace data2 rst outz mem ifsel boot 0 gnd p 1 _ rd_p p 1 _ sd_p gnd p 1 _td_ out_p p14 p13 p30 p33 p37 xt2 u t p50 p51 p52 trace data1 jtag sel ponrz vdd15 gnd vdd15 vddq_ pecl_b 1 p11 p16 p15 oscth p34 p36 gnd xt1 t r p 1 vdd arxtx agnd gnd nmiz trace data3 bus32 en hif sync hwrz sel vdd33 gnd p17 p10 gnd vdd15 p27 p26 p25 p24 r p p 1 _ rx_n p 1 _ rx_p vdd15 p57 tmode 0 tmc2 admux mode memc sel gnd tdi tms pll_ vdd pll_ gnd tdo p21 p23 p22 p02 p n p 1 _ tx_n p 1 _ tx_p agnd p46 tmode 1 gnd vdd33 g nd vdd33 gnd gnd vdd33 gnd gnd p20 p01 p03 p04 n m vdd acb ext res atp p45 tmode 2 vdd33 gnd vdd10 vdd10 vdd10 vdd10 gnd vdd33 trstz p00 p06 p05 p07 m l vdd apll vssa pllcb agnd p42 p47 gnd vdd10 gnd gnd gnd gnd vdd10 gnd tck p64 p66 p67 vdd15 l k p 0 _ t x_n p 0 _ tx_p vdd33 esd p41 p44 gnd vdd10 gnd gnd gnd gnd vdd10 gnd p65 p63 gnd gnd bvdd k j p 0 _ rx_n p 0 _ rx_p vdd15 rdz p40 vdd33 vdd10 gnd gnd gnd gnd vdd10 gnd vdd33 p62 test1 gnd lx j h p 0 vdd arxtx agnd gnd csz0 p43 gnd vdd10 gnd gnd gnd gnd vdd10 gnd vdd33 p60 test2 agnd_ reg bgnd h g busclk wrstbz wrz0 wrz1 a14 vdd33 gnd vdd10 vdd10 vdd10 vdd10 gnd vdd33 gnd p73 p61 avdd_ reg fb g f a2 a3 a4 a5 a15 gnd vdd33 gnd gnd vdd33 gnd vdd33 gnd gnd p72 p71 p70 test3 f e a6 a7 a8 a9 a16 d8 gnd tmc1 gnd vdd3 3 gnd gnd gnd vdd33 p77 p76 p75 p74 e d a10 a11 a12 a13 d7 d9 vdd15 d15 rp22 rp26 rp30 rp31 rp06 gnd rp04 rp02 rp01 rp00 d c a17 a18 a19 a20 d10 d11 d14 rp27 vddq_ pecl_b 0 vdd33 rp20 rp32 rp07 vdd15 rp05 rp03 rp16 rp17 c b d0 d1 d3 d5 d12 rp21 rp24 p 0 _ rd_p p 0 _ sd_p gnd p 0 _td_ out_p test dout5 rp33 rp35 rp10 rp12 rp14 rp15 b a gnd d2 d4 d6 d13 rp23 rp25 p 0 _ rd_n p 0 _ sd_n vdd15 p 0 _td_ out_n p 0 _fx_ en_out rp34 rp36 rp37 rp11 rp13 gnd a 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 r - in32m3 series data sheet 2 . pin information r18ds0008ej0204 page 13 of 100 dec 25, 2014 2.2 pin placement (r - in 32m3 - cl top view) 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 v gnd trace clk trace data2 resetz cci_clk 2_097m ccm_cl k80m p03 p07 p23 p24 p10 p14 p17 p32 gnd xt2 xt1 gnd v u p53 nmiz trace data1 rst outz hwrz sel boot0 p02 p06 p22 p25 p11 p15 p30 p33 p35 p37 eth1_ rxd7 clkout 25m1 u t p54 p55 trace data0 jtag sel memif sel boot1 p01 p05 p21 p26 p12 p16 p31 p34 p36 eth1_ rxd6 eth1_ rxd5 eth1_ rxd4 t r p52 p57 p56 trace data3 ponrz hif sync p00 p04 p20 p27 p13 tdi tms tdo eth1_ rxd3 eth1_ rxd2 eth1_ r xd1 eth1_ rxd0 r p p66 p67 p50 p51 bus32 en tmc2 admux mode memc sel gnd gnd gnd pll_ vdd pll_ gnd oscth eth1_ rxdv eth1_ rxer eth1_ crs eth1_ rxc p n p62 p63 p64 p65 hot resetz gnd vdd33 gnd vdd33 gnd gnd vdd33 gnd gnd trstz eth1_ col eth1_ ge_int eth1_ txc n m p76 p77 p60 p61 tmode 0 vdd33 gnd vdd10 vdd10 vdd10 vdd10 gnd vddq_ mii gnd tck eth1_ txer eth1_ txen eth1_ gtxc m l gnd p73 p74 p75 tmode 1 gnd vdd10 gnd gnd gnd gnd vdd10 gnd vdd33 eth1_ txd0 eth1_ txd1 eth1_ txd2 eth1_ txd3 l k p47 p70 p71 p 72 tmode 2 gnd vdd10 gnd gnd gnd gnd vdd10 vddq_ mii gnd eth1_ txd4 eth1_ txd5 eth1_ txd6 eth1_ txd7 k j p43 p44 p45 p46 gnd vdd33 vdd10 gnd gnd gnd gnd vdd10 gnd gnd eth0_ rxd4 eth0_ rxd5 eth0_ rxd6 eth0_ rxd7 j h busclk p42 p41 p40 gnd gnd vdd10 gnd gn d gnd gnd vdd10 gnd vdd33 eth0_ rxd0 eth0_ rxd1 eth0_ rxd2 eth0_ rxd3 h g rdz csz0 wrstbz wrz0 gnd vdd33 gnd vdd10 vdd10 vdd10 vdd10 gnd vddq_ mii gnd eth_ mdc eth0_ ge_int eth0_ rxer eth0_ rxdv g f wrz1 a2 a3 a4 gnd gnd vdd33 gnd gnd vdd33 gnd vdd33 gnd gnd eth0_ crs eth0_ col eth_ mdio eth0_ txc f e a5 a6 a7 a8 gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd eth0_ txd0 eth0_ txen eth0_ txer eth0_ rxc e d a9 a10 a11 a12 d3 d7 d11 tmc1 rp20 rp31 rp35 rp12 rp16 rp06 eth0_ txd3 eth0_ txd2 eth0_ txd1 eth0_ gtxc d c a13 a14 a15 a16 d4 d8 d12 d15 rp21 rp30 rp34 rp11 rp15 rp07 rp03 eth0_ txd6 eth0_ txd5 eth0_ txd4 c b a17 a18 a19 d1 d5 d9 d13 rp22 rp24 rp27 rp33 rp37 rp14 rp10 rp04 rp01 eth0_ txd7 clkout 25m0 b a gnd a20 d0 d2 d6 d10 d14 rp23 rp25 rp26 rp32 rp36 rp 13 rp17 rp05 rp02 rp00 gnd a 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 r - in32m3 series data sheet 2 . pin information r18ds0008ej0204 page 14 of 100 dec 25, 2014 2.3 signals by function 2.3.1 ethernet signal s (1) phy interface (r - in32m3 - cl only) caution t h e s e signals apply to r - in32m3 - c l only . pin name i/o function active level during reset eth0 _txc i ethernet 0 10m/100m transmit clock port (2.5mhz/25mhz) - eth0_gtxc o ethernet 0 1g transmit clock port (125mhz) - note eth0_txen o ethernet 0 transmit enable port high low eth0_txer o ethernet 0 transmit error port high low eth0_txd0 - eth0_txd7 o ethernet 0 transmit data port - low eth0_ge_int i ether net 0 phy interrupt port high/low - eth0_rxc i ethernet 0 receive clock port - eth0_rxdv i ethernet 0 receive enable port high - eth0_rxer i ethernet 0 receive error port high - eth0_rxd0 - eth0_rxd7 i ethernet 0 receive data port - - eth0_crs i ethe rnet 0 carrier sense port high - eth0_col i ethernet 0 collision port high - eth1_txc i ethernet 1 10m/100m transmit clock port (2.5mhz/25mhz) - eth1_gtxc o ethernet 1 1g transmit clock port (125mhz) - note eth1_txen o ethernet 1 transmit enable po rt high low eth1_txer o ethernet 1 transmit error port high low eth1_txd0 - eth1_txd7 o ethernet 1 transmit data port - low eth1_ge_int i ethernet 1 phy interrupt port high/low - eth1_rxc i ethernet 1 receive clock port - eth1_rxdv i ethernet 1 recei ve enable port high - eth1_rxer i ethernet 1 receive error port high - eth1_rxd0 - eth1_rxd7 i ethernet 1 receive data port - - eth1_crs i ethernet 1 carrier sense port high - eth1_col i ethernet 1 collision port high - eth_mdc o ethernet serial manage ment interface clock low eth_mdio i/o ethernet serial management interface data input/output - hi - z note out put the 125mhz clock. r - in32m3 series data sheet 2 . pin information r18ds0008ej0204 page 15 of 100 dec 25, 2014 (2) media interface (r - in32m3 - ec only) caution t h e s e signals apply to r - in32m3 - e c only . pin name i/o function active level during reset p0_rx_p i phy0 receive data (+) - - p0_rx_n i phy0 receive data ( - ) - - p1_rx_p i phy1 receive data (+) - - p1_rx_n i phy1 receive data ( - ) - - p0_tx_p o phy0 transmit data (+) - - p0_tx_n o phy0 transmit data ( - ) - - p1_tx_p o phy1 transmit data ( +) - - p1_tx_n o phy1 transmit data ( - ) - - p 0 _ s d_ p i phy0 100base - fx signal detect (+) high - p 0 _ s d_n i phy0 100base - fx signal detect ( - ) low - p 1 _ s d_ p i phy1 100base - fx signal detect (+) high - p 1 _ s d_n i phy1 100base - fx signal detect ( - ) low - p 0 _r d_ p i phy0 100base - fx receive data (+) - - p 0 _rd_n i phy0 100base - fx receive data ( - ) - - p 1 _rd_ p i phy1 100base - fx receive data (+) - - p 1 _rd_n i phy1 100base - fx receive data ( - ) - - p 0 _ t d_ out_p o phy0 100base - fx transmit data (+) - - p 0 _ t d_ out_ n o p hy0 100base - fx transmit data ( - ) - - p 1 _ t d_ out_p o phy1 100base - fx transmit data (+) - - p 1 _ t d_ out_ n o phy1 100base - fx transmit data ( - ) - - p0_fx_en_out o phy0 100base - fx fx enable indication 1 100base - fx mode high - p1_fx_en_out o phy1 100base - fx fx enable indication 1 100base - fx mode high - remark in mdi - x mode , the input and output attribute s of txp/txn and rxp/rxn are r e versed . r - in32m3 series data sheet 2 . pin information r18ds0008ej0204 page 16 of 100 dec 25, 2014 (3) other signals pin name i/o function shared port active l evel during reset phylink0, phylink1 i phy link port note1 (for etherswitch) p06 - p07 high hi -z with internal pull - up resistor p0linkledz o sip_phy0 link status led port note p06 low hi -z p1linkledz o sip_phy1 link status led port note p07 low ethsws ecout o etherswitch ivent par 1sec output port p24 high hi -z with internal pull - up resistor p0duplexled z o sip_phy0 half - duplex status led port note2 p70 - p0speed100led z o sip_phy0 100 - base status led port note2 p72 low p0speed10led z o sip_phy0 10 - ba se status led port note2 p73 low p 1 duplexled z o sip_phy1 half - duplex status led port note2 p74 - p 1 speed100led z o sip_phy1 100 - base status led port note2 p76 low p 1 speed10led z o sip_phy1 10 - base status led port note2 p77 low p0 act led z o sip_phy0 r x status led port note2 rp02 low p 1act led z o sip_phy1 tx status led port note2 rp04 low note1. support ed only by r - in32m3 - cl note2. support ed only by r - in32m3 - ec r - in32m3 series data sheet 2 . pin information r18ds0008ej0204 page 17 of 100 dec 25, 2014 2.3.2 ethercat slave controller signal s (r - in32m3 - ec only) caution t h e s e signals apply to r - in32m3 - e c only . pin name i/o function shared port active level during reset catledrun o ether cat run led port p00 high hi -z catirq o ether cat irq port p01 high catledster o ether cat dual - color state led port p02 high catlederr o ether cat error led port p03 high catlinkact0, catlinkact1 o ether cat link / activity led port p04 - p05 high catsync1 o ether cat sync1 port p10 high hi -z with internal pull - up resistor catsync0 o ether cat sync0 port p11 high hi -z with internal pull - down resis tor catlatch1 i ether cat latch1 port p10 high hi -z with internal pull - up resistor catlatch0 i ether cat latch0 port p11 high hi -z with internal pull - down resistor cati2cclk o ether cat eeprom i2c clock port p22 - hi -z cati2cdata i/o ether cat eeprom i 2c data port p23 - catrestout o ether cat phy resetout port p56 - hi -z with internal pull - up resistor r - in32m3 series data sheet 2 . pin information r18ds0008ej0204 page 18 of 100 dec 25, 2014 2.3.3 external memory interface signal s pin name i/o function shared signal shared port active level during reset busclk o bus clock output port - - - - cs z0 o c hip select signal output port hcsz - low hi -z with internal pull - up resistor csz1 o hpgcsz p44 csz2 o - p51 csz3 o - p50 a1 o address output port ha1 p40 - hi -z with internal pull - up resistor a 2 - a 20 o ha2 - ha20 - hi -z with internal pull - down resistor a21 - a27 o - rp21 - rp27 d0 - d15 note1 i/o data bus port hd0 - hd15 - d16 - d31 note1 i/o hd16 - hd31 rp30 - rp37 rp10 - rp17 - hi -z with internal pull - up resistor r dz o read strobe output port hrdz - low hi -z with internal pull - up resist or wrstbz o write strobe output port hwrstbz - low wrz0, wrz1/ benz0, benz1 o effectively byte lane strobe output port hwrz0, hwrz1 / hbenz0, hbenz1 - low wrz2, wrz3/ benz2, benz3 o hwrz2, hwrz3 / hbenz2, hbenz3 rp06 rp07 waitz i wait signal input port hwaitz p41 low hi -z with internal pull - up resistor waitz1 - waitz3 note2 - p45 - p47 bcystz / advz note3 o address valid output port hbcystz rp20 low hi -z with internal pull - up resistor remark external memory i nterface signal expects busclk is an i nput signal while the internal reset signal (hresetz) is active. note1. when using synchronous burst access memc this port is shared with address port when admuxmode is high . note 2. this port is available only w hen using synchronous burst access memc. note 3. this port functions as bcystz when using as ynchronous sram memc , it functions as advz when using synchronous burst access memc r - in32m3 series data sheet 2 . pin information r18ds0008ej0204 page 19 of 100 dec 25, 2014 2.3.4 external m p u interface signal s pin name i/o function shared signal shared p ort active level during reset hbusclk i bus clock for host mp u output port intpz11 p43 - hi -z with internal pull - up resistor hcsz i chip select signal in put port cs z0 - low hpgcsz i pogrom mode chip select signal in put port csz1 p44 low hwaitz o wait signal out put port waitz p41 low ha1 i address in put port a1 p40 - hi -z with internal pull - up resistor ha2 - ha20 i a 2 - a 20 - hi - z with internal pull - down resistor hd0 - hd15 i/o data bus port d0 - d15 - - hd16 - hd31 i/o d16 - d31 rp30 - rp37 rp10 - rp17 hi - z with internal pull - up resistor hrdz i read strobe input port r dz - low hi -z with internal pull - up resistor hwrstbz i write strobe output port wrstbz - low hwrz0, hwrz1/ hbenz0,hbenz1 i effectively byte lane strobe in put port wrz0, wrz1/ benz0, be nz1 - low hwrz2, hwrz3/ hbenz2,hbenz3 i wrz2, wrz3/ benz2, benz3 rp06 rp07 herroutz o error interrupt output port sleeping p42 low high hbcystz i bus cycle input port bcystz / advz rp20 low hi -z with internal pull - up resistor caution when you use asynchronous mode, please input low into a hbusclk pin. . remark ex ternal m p u i nterface s ignal s operate as an external m p u interface durinug reset . r - in32m3 series data sheet 2 . pin info rmation r18ds0008ej0204 page 20 of 100 dec 25, 2014 2.3.5 port signal s and real - time p ort signal s port signal s and real - time port signal s are configured as 12 sets of 8 - bit port s . t hey are able to realize 32 - bit access by grouping 4 ports ; i.e. port s 0 - 3, port s 4 - 7 or r eal - time port s 0 - 3. (1/4) port name m ode 1 m ode 2 m ode 3 m ode 4 level during reset p0 p00 intpz0 catledrun note1 cci_runledz note2 - hi -z r - in32m3- ec: hi - z (without internal resistor) r - in32m3- cl: with internal pu ll -up resistor p01 intpz1 catirq note1 - - p02 intpz2 catledster note1 cci_dlinkledz note2 - p03 intpz3 catlederr note1 cci_errledz note2 ccs_mon5 p04 intpz4 catlinkact0 note1 cci_lerr1ledz note2 ccs_mon6 p05 intpz5 catlinkact1 note1 cci_ler r2ledz note2 ccs_mon7 p06 phylink0 note2 p0linkledz note1 cci_sdledz note2 ccs_mon0 p07 phylink1 note2 p1linkledz note1 cci_rdledz note2 ccs_resout p1 p10 catlatch 1 note1 catsync 1 note1 - ccs_refstb hi -z with internal pull -up resistor p11 catlatc h 0 note1 catsync 0 note1 - ccs_mon4 hi -z with internal pull - down resistor p12 intpz6 - cci_nmiz note2 - hi -z with internal pull -up resistor p13 intpz7 - cci_wdtiz note2 / ccs_wdtz / ccm_wdtenz - p14 smsck - - - p15 sms i - - - p16 sms o - - - p17 smcsz - - - p2 p20 rxd0 - ccm_linkerrz - hi -z r - in32m3- ec: hi - z (without internal resistor) r - in32m3- cl: with internal pull -up resistor p21 txd0 - ccm_errz - p22 intpz 8 cati2cclk note1 ccs_iotensu - p23 intpz 9 cati2cdata note1 ccs_senyu0 - p24 intpz 10 ethswsecout ccs_senyu1 - p25 wdtoutz - ccs_errz - p26 tin 1 tout 1 ccm_ run z / ccs_ run z - p27 tin 0 tout 0 - - note1. only used by r - in32m3 - ec . note2. only used by r - in32m3 - cl . r - in32m3 series data sheet 2 . pin information r18ds0008ej0204 page 21 of 100 dec 25, 2014 (2/4) port name m ode 1 m ode 2 m ode 3 m ode 4 lev el during reset p3 p30 rxd1 - - - hi -z with internal pull -up resistor p31 txd1 - - - p32 dmareq z1 - - ccs_mon1 p33 dmaackz 1 cci_ waitedgeh note2 - ccs_mon2 p34 dmatcz 1 cci_ wrlenh note2 - ccs_mon3 p35 csisck1 intpz22 ccm_irz - p36 csisi 1 intpz23 ccs_fusez - p37 csiso1 intpz24 ccm_mstz - p4 p40 a1 ha1 - - hi -z i pull - up ? ??? p41 waitz hwaitz - - p42 sleeping herroutz ccm_ sdgc z - p43 intpz 11 hbusclk - - p44 csz1 hpgcsz - - p45 csisck0 waitz1 - - p46 csisi0 wait z2 - - p47 csiso0 waitz3 - - p5 p50 csz3 - ccm_lnkrunz / ccs_lnkrunz - p51 csz2 - ccm_rdledz / ccs_rdledz - p52 tin3 tout3 ccs_ sdgateon - hi -z with internal pull - down resistor p53 crxd0 ccs_rd ccm_ rd - hi -z with internal pull -up resistor p54 ctxd0 ccs_sd ccm_ sd - p55 crxd1 - - - p56 ctxd1 catrestout note1 cci_phyrez1 note2 - p57 tin2 tout2 cci_ phyrez0 note2 - note1. only used by r - in32m3 - ec. note2. only used by r - in32m3 - cl. r - in32m3 series data sheet 2 . pin information r18ds0008ej0204 page 22 of 100 dec 25, 2014 ( 3/4) port name m ode 1 m ode 2 m ode 3 m ode 4 leve l during reset p6 p60 scl0 - - - hi -z r - in32m3- ec: hi - z (without internal resistor) r - in32m3- cl: with internal pull - up resistor p61 sda0 - - - p62 rt dmareqz - ccm_mdin0 - p63 rt dmaackz - ccm_mdin1 - p64 rt dmatcz - ccm_mdin2 - p 65 dmareqz0 - ccm_mdin3 - p66 dmaackz0 - cci_intz note2 - p67 dmatcz0 - - - p7 p70 csics00 p0 duplexled z note1 ccs_ station _ no_0 / ccm_snin0 - p71 csics01 - ccs_ station_no_1 / ccm_snin1 - p72 csics10 p0speed100led z note1 ccs_ station_no_2 / ccm_ snin2 - p73 csics11 p0speed10led z note1 ccs_ station_no_3 / ccm_snin3 - p74 intpz12 p1duplexled z note1 ccs_ station_no_4 / ccm_snin4 - p75 intpz13 - ccs_ station_no_5 / ccm_snin5 - p76 intpz14 p1speed100led z note1 ccs_ station_no_6 / ccm_snin6 - p77 intpz15 p1speed10led z note1 ccs_ station_no_7 / ccm_snin7 - note1. only used by r - in32m3 - ec. note2. only used by r - in32m3 - cl. r - in32m3 series data sheet 2 . pin information r18ds0008ej0204 page 23 of 100 dec 25, 2014 rp0x - rp3x are real - time port s which can transfer data via a dedicated dma comtroller, and are unaffected by bus con gestion. t hey are able to perf or m input and output of the port by 32 bit unit in sync with dma transfer trigger by dma controller for exclusive use of the r eal - time port . ( 4/4) port name m ode 1 m ode 2 m ode 3 m ode 4 level during reset rp0 r p00 intpz 16 scl1 ccm_sdledz / ccs_sdledz - hi -z with internal pull -up resistor rp01 intpz17 sda1 ccm_smstz - rp02 intpz18 p0actledz note ccs_bs1 - rp03 intpz19 - ccs_bs2 - rp04 intpz20 p1actledz note ccs_bs4 - rp05 intpz21 - ccs_bs8 - rp06 wrz2/benz2 hwrz2/hbenz2 - - rp07 wrz3/benz3 hwrz3/hbenz3 - - rp1 rp10 d24/hd24 - - - hi -z with internal pull -up resistor rp11 d25/hd25 - - - rp12 d26/hd26 - - - rp13 d27/hd27 - - - rp14 d28/hd28 - - - rp15 d29/hd29 - - - rp16 d30/hd30 - - - rp17 d31/hd31 - - - rp2 rp20 bcystz / advz hbcystz - - hi -z with internal pull -up resistor rp21 a21 - - - hi -z with internal pull - down resistor rp22 a22 - - - rp23 a23 - - - rp24 a24 intpz25 - - rp25 a2 5 intpz26 - - rp26 a26 intpz27 - - rp27 a27 intpz28 - - rp3 rp30 d16/hd16 - - - hi -z with internal pull -up resistor rp31 d17/hd17 - - - rp32 d18/hd18 - - - rp33 d19/hd19 - - - rp34 d20/hd20 - - - rp35 d21/hd21 - - - r p36 d22/hd22 - - - rp37 d23/hd23 - - - note only used by r - in32m3 - ec . r - in32m3 series data sheet 2 . pin information r18ds0008ej0204 page 24 of 100 dec 25, 2014 2.3.6 serial flash rom interface signal s the serial flash rom interface supports f ast read, fast read dual output and fast read dual i/o mode. pin name i/o function shared port acti ve level during reset smsck o serial clock output port for serial flash rom p14 / hi -z with internal pull - up resistor sms i i/o serial data port for serial flash rom (connect to so of serial flash rom ) p15 high sms o i/o serial data port for serial f lash rom (connect to si of serial flash rom ) p16 high smcsz o chip select output port for serial flash rom p17 low 2.3.7 dma interface signal s there are two dma controllers: one with four internal chan nels but only two external interfaces , and one with one internal channel and one external interce as r eal - time dma controller . pin name i/o function shared port active level during reset rt dmareqz i rtdmac dma transfer request port p 62 low hi -z r - in32m3- ec: hi - z (without internal resistor) r - in32m3- cl: with internal pull - up resistor rt dmaackz o rtdmac dma acknowledge output port p63 low rt dmatcz o rtdmac t erminal count output port p 64 low dmareqz0 i dma transfer request port 0 p 65 low dmaackz0 o dma acknowledge output port 0 p 66 low dmatcz0 o dma t er minal count output port 0 p 67 low dmareqz1 i dma transfer request port 1 p 32 low hi -z with internal pull - up resistor dmaackz1 o dma acknowledge output port 1 p 33 low dmatcz1 o dma t erminal count output port 1 p 34 low caution each dma interface is assigned to a specific dma channel. dma channel 0 = interface 0 (dmareqz0, dmaackz0, dmatcz0) dma channel 1 = interface 1 (dmareqz1, dmaackz1, dmatcz1) dma channels 2, 3 = no external interface r - in32m3 series data sheet 2 . pin information r18ds0008ej0204 page 25 of 100 dec 25, 2014 2.3.8 external interrupt input signal s pin name i/o function shar ed port active level during reset nmiz i n on- maskable external interrupt input port - low hi -z high level by internal pull - up register intpz0 - intpz5 i external interrupt input port p00 - p05 low hi -z r - in32m3- ec: hi - z (without internal resistor) r - in32m 3 - cl: with internal pull - up resistor intpz6, intpz7 p12,p13 low hi -z with internal pull - up resistor intpz8 - intpz10 p22 - p24 low hi -z r - in32m3- ec: hi - z (without internal resistor) r - in32m3- cl: with internal pull - up resistor intpz11 p43 low hi -z with internal pull - up resistor intpz12 - intpz15 p74 - p77 low hi -z r - in32m3- ec: hi - z (without internal resistor) r - in32m3- cl: with internal pull - up resistor intpz16 - intpz21 rp00 - rp05 low hi -z with internal pull - up resistor intpz22 - intpz24 p35 - p37 intp z25 - intpz28 rp24 - rp27 hi -z with internal pull - down resistor r - in32m3 series data sheet 2 . pin information r18ds0008ej0204 page 26 of 100 dec 25, 2014 2.3.9 timer i/o signal s pin name i/o function shared port active level during reset tin0 / tout0 i/o timer tauj0 port p27 - hi -z r - in32m3- ec: hi - z (without internal resistor) r - in32m3- cl: with in ternal pull - up resistor tin1 / tout1 i/o timer tauj1 port p26 - tin2 / tout2 i/o timer tauj2 port p57 - hi -z with internal pull - up resistor tin3 / tout3 i/o timer tauj3 port p52 - hi -z with internal pull - down resistor 2.3.10 watch d og timer output signal pin name i/o function shared port active level during reset wdtoutz o watchd og timer output port p25 low hi -z r - in32m3- ec: hi - z (without internal resistor) r - in32m3- cl: with internal pull - up resistor 2.3.11 trace signal s pin name i/o function active level during reset traceclk o trace port clock output port - - tracedata3 - tracedata0 o trace port data output port - low 2.3.12 cpu power control signal pin name i/o function shared port active level during reset sleeping o cpu sleep mode output port p42 high hi -z with internal pull - up resistor r - in32m3 series data sheet 2 . pin information r18ds0008ej0204 page 27 of 100 dec 25, 2014 2.3.13 serial interface signal s pin name i/o function shared port active level during reset txd0 o uart0 serial data output port p 21 - hi -z r - in32m3- ec: hi - z (without internal resistor) r - in32m3- cl: with internal pull - up resistor r xd0 i uart0 serial data input port p20 - txd1 o uart1 serial data output port p 31 - hi -z with internal pull - up resistor rxd1 i uart1 serial data input port p 30 - csisck0 i/o csi0 serial clock port p45 - csisi0 i csi0 serial data input port p46 - c siso0 o csi0 serial data output port p47 - csics00 , csics0 1 o csi0 chip select 0,1 port p70, p71 low hi -z r - in32m3- ec: hi - z (without internal resistor) r - in32m3- cl: with internal pull - up resistor csisck1 i/o csi1 serial clock port p35 - hi -z with interna l pull - up resistor csisi1 i csi1 serial data input port p 36 - csiso1 o csi1 serial data output port p 37 - csics 1 0 , csics 11 o csi1 chip select 0,1 port p72, p73 low hi -z r - in32m3- ec: hi - z (without internal resistor) r - in32m3- cl: with internal pull - up re sistor scl0 i/o i2c0 serial clock port p 60 - sda0 i/o i2c0 serial data port p6 1 - scl1 i/o i2c1 serial clock port rp00 - hi -z with internal pull - up resistor sda1 i/o i2c1 serial data port rp01 - crxd0 i can0 receive data port (5v - tolerant buffer) p53 - ctxd0 o can0 transfer data port p 54 - crxd1 i can1 receive data port (5v - tolerant buffer) p55 - ctxd1 o can1 transfer data port p 56 - r - in32m3 series data sheet 2 . pin information r18ds0008ej0204 page 28 of 100 dec 25, 2014 2.3.14 cc- link ie field (intelligent device station ) signal s (r - in32m3 - cl only) pin name i/o function shared po rt active level during reset cci_runledz o run led control port p00 low hi -z with internal pull - up resistor cci_dlinkledz o cyclic communication status check led control port p02 low cci_errledz o field network error led control port p03 low cci_ler r1ledz o link error led control port 1 p04 low cci_lerr2ledz o link error led control port 2 p05 low cci_sdledz o transfer data led control port p06 low cci_rdledz o receive data led control port p07 low cci_nmiz o output nmi interrupt to mp u p12 low hi -z with internal pull - up resistor cci_wdtiz i input from watchd og timer p13 low cci_ waitedgeh i/o wait synchroniz ed edge setting 0 rise edge mode 1 low edge mode p33 - cci_ wrlenh i/o wrl enable setting 0 byte write enable mode 1 byte enable mod e p34 - cci_phyrez1 o phy reset output 1 port p56 low cci_ phyrez 0 o phy reset output 0 port p57 low cci_ intz o o utput i nterrupt signal to mp u p66 low cci_clk2_097m i 2.097152mhz clock - - - r - in32m3 series data sheet 2 . pin information r18ds0008ej0204 page 29 of 100 dec 25, 2014 2.3.15 cc- link signals ( intelligent device station) pin n ame i/o function shared port active level during reset ccm_linkerrz o link error led control port p20 low hi -z r - in32m3- ec: hi - z (without internal resistor) r - in32m3- cl: with internal pull - up resistor ccm_errz o e rror led control port p21 low ccm_ run z o run led control port p26 low ccm_ mdin0 - ccm_mdin3 i mode setting switch input port p62 - p65 - ccm_ snin0 - ccm_ snin7 i station no. setting switch port p70 - p77 - ccm_ lnkrunz o link run led control port p50 low hi -z with internal pull - up resistor ccm_ r dledz o receive data led control port p51 low ccm_ sdledz o transfer data led control port rp00 low ccm_ irz o i nterrupt output port p35 low ccm_ wdtenz i watch d og timer error input port p13 low ccm_ mstz o operation check led port p37 low ccm_ smstz o stand - by master led control port rp01 low ccm_ rd i data receive port p53 - ccm_ sd o d ata transfer port p54 - ccm_ sdgc z o transfer data & gate control port p42 low ccm_clk80m i cc - link clock - - - r - in32m3 series data sheet 2 . pin information r18ds0008ej0204 page 30 of 100 dec 25, 2014 2.3.16 cc- link signals (remote device station) cautio n to use a remote device station, it is necessary to connect a ccs_refstb pin t o an external interrupt pin (intpz). pin name i/o function shared port active level during reset ccs_mon1 - ccs_mon3 o m onitor port p32 - p34 - hi -z with internal pull - up resis tor ccs_mon4 o m onitor port p11 - hi -z with internal pull - down resistor ccs_mon0 o m onitor port p06 - hi -z r - in32m3- ec: hi - z (without internal resistor) r - in32m3- cl: with internal pull - up resistor ccs_mon5 - ccs_mon7 o m onitor port p03 - p05 - ccs_ resou t o reset port p07 high ccs_iotensu i initial setting port p22 - ccs_senyu0 i initial setting port p23 - ccs_senyu1 i initial setting port p24 - ccs_errz o operation check led port p25 low ccs_ run z o operation check led port p26 low ccs_ statio n _ no_0 - ccs_ station _ no_7 i station no. setting switch port p70 - p77 - ccs_lnkrunz o link run led control port p50 low hi -z with internal pull - up resistor ccs_ refstb o interrupt port p10 high ccs_wdtz i watchd og timer port p13 low ccs_ rdledz o receive data led control port p51 low ccs_ rd i data receive port p53 - ccs_ sd o d ata transfer port p54 - ccs_sdledz o operation check led port rp00 low ccs_sdgateon o transfer data & gate control port p52 high hi -z with internal pull - down resistor ccs_bs 1 i b aud rate setting switch port rp02 - hi -z with internal pull - up resistor ccs_bs2 i b aud rate setting switch port rp03 - ccs_bs4 i b aud rate setting switch port rp04 - ccs_bs8 i b aud rate setting switch port rp05 - ccs_fusez i fuse cutting signal port p36 low ccm_clk80m i cc - link operation lock - - - r - in32m3 series data sheet 2 . pin information r18ds0008ej0204 page 31 of 100 dec 25, 2014 2.3.17 system signal s pin name i/o function active level during reset xt1 i crystal oscillator ports for system clock *o s cillator output connects to x2 for direct connection . - - xt2 i/o - - reset z i reset input port low - hotresetz note1 i hot reset input port low ponrz i internal ram power on reset input port low - oscth i input high level when external clock input mode - - jtagsel i jtag operation mode setting port - - rstoutz o reset to external circuit output port low - clkout25m0 o phy clock output port clkout25m1 o phy clock output port pll_vdd - pll power supply (1.0v) - - pll_gnd - pll power ground supply (gnd) - - vdd33 - i/o power supply ( 3.3 v) - - vdd10 - internal power supply (1.0v) - - gnd - ground supply (gnd) - - vddq_mii note1 - ethernet i/o power supply ( 3.3 v) - - lx note2 o r egulator 1.5v power output extres note2 - reference resistor for etherphy connect port p 0 vddarxtx note2 - analog port rx/t x power supply (1.5v) - port 0 - - p 1 vddarxtx note2 - analog port rx/tx power supply (1.5v) - port 0 - - vddacb note2 - etherphy analog central power supply (3.3v) - - agnd note2 - etherphy analog ground supply (gnd) - - vdd15 note2 - etherphy power s upply (1.5 v ) - - vddapll note2 - etherphy analog central power supply (1.5v) - - vssapllcb note2 - etherphy analog central ground supply (gnd) - - vdd33esd note2 - etherphy analog test power supply (3.3v) - - avdd_reg note2 - regulator analog power sup ply (3.3v) - - agnd_reg note2 - regulator analog ground supply (gnd) - - bvdd note2 - regulator power supply ( 3.3 v) - - bgnd note2 - regulator ground supply (gnd) - - fb note2 i r - in32m3 series data sheet 2 . pin informat ion r18ds0008ej0204 page 32 of 100 dec 25, 2014 2.3.18 test signal s pin name i/o function active level during reset tmode0 - tmode2 i test mode select port - - tms i/o j tag mode select port - - tdi i jtag serial data input port - - tdo o jtag serial data output port - - trstz i jtag reset port low - tck i jtag clock input port - - atp note i renesas test port s tmc1 i - - tmc2 i - - test1 note i - - test2 not e i - - test3 note i - - testout5 note o - - note only applies to r - in32m3 - ec . r - in32m3 series data sheet 2 . pin information r18ds0008ej0204 page 33 of 100 dec 25, 2014 2.3.19 operation m ode setting signal pin name i/o function active level during reset boot1 - boot0 i boot mode select port 00 : external memory boot 01 : external serial flas h rom boot 10 : external mp u boot 11 : i nstruction ram boot( debugger used only) - - memifsel i external memory interface select port 0 : slave memory interface 1 : external mp u interface - - bus32en i external memory interface bus width select port 0 : 16bit bus 1 : 32bit bus - - hifsync i external mp u i/f operation mode select port 0 : asynchronous sram interface 1 : synchronous sram interface - - hwrzsel i external m pu interface hwrz/hbenz select port 0 : hbenz use 1 : hwrz use - - memcsel i interna l memory controller select port 0 : asynchronous sram memc 1 : synchronous burst access memc - - admuxmode note i multiplex of address / data port note 0 : separate 1 : multiplex of address / data - - note admuxmode port is only available when memcsel port is high ( which select s synchronous burst access memc) . the asynchronous sram memc does not support address/data multiplexing. r - in32m3 series data sheet 2 . pin information r18ds0008ej0204 page 34 of 100 dec 25, 2014 2.4 buffer type s and recommended connection s for unused pins 2.4.1 ethernet signal s (1) phy interface signal s caution these signals apply to r - in32m3 - cl only. pin name i/o interface recommended connection when not in use eth0_txc i input buffer (3.3v) connect to gnd eth0_gtxc o bid_buf(3.3v_gmii_mii)_with_iolh _control open eth0_txen eth0_txer eth0_txd0 - eth0_txd7 eth0_ ge_int i input buffer (3.3v) connect to gnd eth0_rxc i bid_buf (3.3v_gmii_mii)_with_iolh _control connect to gnd eth0_rxdv eth0_rxer eth0_rxd0 - eth0_rxd7 eth0_crs i input buffer (3.3v) connect to gnd eth0_col eth1_txc eth1_gtxc o bid_ buf (3.3v_gmii_mii)_with_iolh _control open eth1_txen eth1_txer eth1_txd0 - eth1_txd7 eth1_ge_int i input buffer (3.3v) connect to gnd eth1_rxc i bid_buf (3.3v_gmii_mii)_with_iolh _control connect to gnd eth1_rxdv eth1_rxer eth1_rxd0 - e th1_rxd7 eth1_crs i input buffer (3.3v) connect to gnd eth1_col eth_mdc o output buffer (3.3v) 6ma open eth_mdio i/o i/o buffer (3.3v) 6ma connect to gnd r - in32m3 series data sheet 2 . pin information r18ds0008ej0204 page 35 of 100 dec 25, 2014 (2) media interface signal s caution these signals apply to r - in32m3 - e c only . pin name i/o interface recommended connection when not in use p0_rx_p i 3.3v analog in put buffer open p0_rx_n i p1_rx_p i p1_rx_n i p0_tx_p o 3.3v analog in put buffer open p0_tx_n o p1_tx_p o p1_tx_n o p 0 _ s d_ p i 3.3v pecl in put buffer connect to g nd p 0 _ s d_n i p 1 _ s d_ p i p 1 _ s d_n i p 0 _rd_ p i p 0 _rd_n i p 1 _rd_ p i p 1 _rd_n i p 0 _ t d_ out_p o 3.3v pecl output buffer open p 0 _ t d_ out_ n o p 1 _ t d_ out_p o p 1 _ t d_ out_ n o p0_fx_en_out o output buffer (3.3v) 12 ma open p1_fx_en_out o 2.4.2 external memory/ mp u interface signal s pin name i/o interface recommended connection when not in use busclk o output buffer (3.3v) 9ma open cs z0 / hcsz i/o i/o buffer (3.3v) 6ma 50k pull - up open a 2 - a 20 / ha2 - ha20 i/o i/o buffer (3.3v) 6ma 50k pull -do wn open d 0 - d 15 / hd0 - hd15 r dz / hrdz i/o i/o buffer (3.3v) 6ma 50k pull -up open wrstbz / hwrstbz wrz0, wrz1 / benz0, benz1 / hwrz0, hwrz1 r - in32m3 series data sheet 2 . pin information r18ds0008ej0204 page 36 of 100 dec 25, 2014 2.4.3 system signal s pin name i/o interface recommended connection when not in use nmiz i input buffer (3.3v) schmitt in 50k pull - up connect to vdd33 (3.3v) xt1 i oscillator with en connect to gnd xt2 - - rstoutz o output buffer (3.3v) 6ma open resetz i input buffer (3.3v) schmitt in - ponrz hotresetz connect to vdd33 (3.3v) oscth i input buff er (3.3v) schmitt in, 50k pull - down - jtagsel 2.4.4 test signal s pin name i/o interface required connection when not in use tmode0 - tmode2 i input buffer (3.3v) schmitt in, 50k pull - down connect to gnd tms i/o i/o buffer (3.3v) 6ma 50k pull - up open t di i input buffer (3.3v) , 50k pull - up open tdo o 3 - state output buffer (3.3v) 6ma open trstz i input buffer (3.3v) schmitt in 50k pull - up open tck i input buffer (3.3v) , 50k pull - down open tmc1 i (tmc1) input buffer (3.3v) for tmc terminal connec t to gnd tmc2 i (tmc2) input buffer (3.3v) for tmc terminal connect to gnd atp note i input buffer (3.3v) open test1 note i input buffer (3.3v) connect to gnd test2 note i input buffer (3.3v) test3 note i input buffer (3.3v) testdout5 note o output buffer (3.3v) open note these signals apply to r - in32m3 - ec only . r - in32m3 series data sheet 2 . pin information r18ds0008ej0204 page 37 of 100 dec 25, 2014 2.4.5 port signal s (1/2) pin name i/o interface recommended connection when not in use p00 - p07 i/o [r - in32m3- ec] i/o buffer (3.3v) (6ma) [r - in32m3- cl] programmable i/o buffer (3.3v) load dr ive select function (6ma, 12ma) resistor select function ( 50k pull - up or 50k pull - down or neither) r - in32m3-ec : connect to gnd r - in32m3-cl : open p10 i/o programmable i/o buffer (3.3v) load drive select function (6ma, 12ma) resistor select function ( 5 0k pull - up or 50k pull - down or neither) open p11 - p17 i/o programmable i/o buffer (3.3v)(6ma) resistor select function ( 50k pull - up or 50k pull - down or neither) open p20 - 21, p25-26 i/o [r - in32m3- ec] i/o buffer (3.3v) (6ma) [r - in32m3- cl] programmable i/o buffer (3.3v) load drive select function (6ma, 12ma) resistor select function ( 50k pull - up or 50k pull - down or neither) r - in32m3-ec : connect to gnd r - in32m3-cl : open p22 - 24, 27 i/o [r - in32m3- ec] i/o buffer (3.3v) (6ma) [r - in32m3- cl] programmable i/o buffer (3.3v) (6ma ) resistor select function ( 50k pull - up or 50k pull - down or neither) p30 , p31 i/o programmable i/o buffer (3.3v) load drive select function (6ma, 12ma) resistor select function ( 50k pull - up or 50k pull - down or neither) open p32 - p36 i/o programmable i/o buffer (3.3v)(6ma) resistor select function ( 50k pull - up or 50k pull - down or neither) p37 i/o programmable i/o buffer (3.3v) load drive select function (6ma, 12ma) resistor select function ( 50k pull - up or 50k pull - down or neither) r - in32m3 series data sheet 2 . pin information r18ds0008ej0204 page 38 of 100 dec 25, 2014 (2/2) pin name i/o interface recommended connection when not in use p40 - p47 i/o programmable i/o buffer (3.3v)(6ma) resistor select function ( 50k pull - up or 50k pull - down or neither) open p50 - p52 i/o programmable i/o buffer (3.3v) load drive select function (6ma, 12ma) resistor select function ( 50k pull - up or 50k pull - down or neither) p53 - p56 i/o 5v - tolerant i/o buffer 4ma 50k pull - up p57 i/o programmable i/o buffer (3.3v)(6ma) resistor select function ( 50k pull - up or 50k pull - down or neither) p60, p65 - p67 i/o [r - in32m3- ec] i/o buffer (3.3v) (6ma) [r - in32m3- cl] programmable i/o buffer (3.3v) (6ma) resistor select function ( 50k pull - up or 50k pull - down or neither) r - in32m3-ec : connect to gnd r - in32m3-cl : open p61 -p64 i/o [r - in32m3- ec] i/o buffer (3.3v) (6ma) [r - in32m3- cl] programmable i/o buffer (3.3v) load drive select function (6ma, 12ma) resistor select function ( 50k pull - up or 50k pull - down or neither) p70 - p77 i/o [r - in32m3- ec] i/o buffer (3.3v) (6ma) [r -i n32m3 - cl] programmable i/o buffer (3.3v) (6ma) resistor select function ( 50k pull - up or 50k pull - down or neither) r - in32m3-ec : connect to gnd r - in32m3-cl : open r p 0 0 - rp07 i/o programmable i/o buffer (3.3v) load drive select function (6ma, 12ma) resis tor select function ( 50k pull - up or 50k pull - down or neither) open r p 10 - rp17 rp 20 - rp27 rp30 - rp37 r - in32m3 series data sheet 2 . pin information r18ds0008ej0204 page 39 of 100 dec 25, 2014 2.4.6 operation m ode s etting signal s pin name i/o interface recommended connection when not in use boot0, boot1 i input buffer (3.3v) schmitt i n - memifsel bus32en hifsync hwrzsel memcsel admuxmode 2.4.7 cc- link ie field ( intelligent device station ) signal (r - in32m3 - cl only) pin name i/o interface recommended connection when not in use cci_clk2_097m i input buffer (3.3v) 2.09 7152mhz clock input caution this pin is needed clock input even if user does not use cc - link ie field function. 2.4.8 cc- link signal ( intelligent device station , remote device station ) pin name i/o interface recommended connection when not in use ccm_clk8 0m i input buffer (3.3v) connect to gnd 2.4.9 trace signal s pin name i/o interface recommended connection when not in use traceclk o output buffer (3.3v) 6ma open tracedata[3:0] r - in32m3 series data sheet 3 . specifications r18ds0008ej0204 page 40 of 100 dec 25, 2014 3. specification s this chapter includes information specific to the r - in32m3 s eries . 3.1 cpu (cortex - m3) the r - in32m3 includes high - efficiency 32 - bit (arm cortex - m3 core) processor. 3.1.1 cpu core i nformation th e version of the cortex - m3 core included in r - in32m3 is shown below. . more information about the architecture of the cpu can be obta ined from: . http://infocenter.arm.com/help/topic/com.arm.doc.set.cortexm/index.html product name core revision r - in32m3 series (r - in32m3 - ec/cl) cortex - m3 r2p1 r - in32m3 series data sheet 3 . specifications r18ds0008ej0204 page 41 of 100 dec 25, 2014 3.1.2 cpu core c onfiguration the cortex - m3 included in r - in32m3 has the following configuration. category configuration item setting remark process process cb90 - mr a rbitrary value interrupts num_irq 128 non - maskable interrupt (nmi) + 1 to 240 physical interrupts interrupt priority levels lvl_width 4 priority bit number 3 to 8 ( 8 to 256 priority levels ) mpu mpu_present yes memory protection is presen t debug level debug_lvl 3 debug level 1 to 3 trace level trace_lvl 2 trace level 0 to 2 sw/swj - dp select jtag_ present swj -dp swj - dp selected in case of jtag access circuit built - in. bit band area bb_present yes bit band function is presen t debug level 1 2 3 (r - in32m3 ? s setting) function outline minimum debug configuration full debug configuration (data match ing function: unavailable) full debug configuration (data matching function: available) debug h alt yes yes yes breakpoints 2 (instruction) 6 (instruction) 2 (literal) 6 (instruction) 2 (literal) dwt c omparator number 1 (data matching function: unavailab le) 4 (data matching function: unavailable) 4 flash patch function no yes yes trace level 0 1 2 (r - in32m3 ? s setting) function outline non - trace standard trace full trace itm, tpiu function no yes yes dwt trigger and counter no yes yes etm function n o no yes caution r - in32m3 does not support sleepdeep mode ; p lease do not set the sleepdeep bit of the scr register to ? 1 ? . r - in32m3 series data sheet 3 . specifications r18ds0008ej0204 page 42 of 100 dec 25, 2014 3.2 giga bit ether net mac 3.2.1 feature s - port number : 1port (2port switch built - in) - 10base, 100base, 1000base mac function - 1000base - x pcs support - full - duplex and half - duplex communication support - automatic p au se packet transmission function - automatic suspend function when receiving pause packet - mii/gmii interface 3.2.2 switch function s r - in32m3 includes the following switch features: - integrated ethernet switch engine - tw o port interfaces with integrated 10/100 or 10/100/1000 mac modules - implements hardware switching, look - up and filtering - qos support with frame priority classification for flexible output queue management - priority c lassification based on vlan priority (ieee802.1q) with priority remapping - optional classification and priority assignment based on ipv4 diffserv code point field, ipv6 class of service - implements 4 priority queues with strict priority on the line interfa ces - support s ethernet multicast, broadcast with flooding control to avoid unnecessary duplication of frames - supports vlan frames reception and transmission (tbd) - cut - through/hub extension module - device level ring (dlr) extension module (tbd) r - in32m3 series data sheet 3 . specifications r18ds0008ej0204 page 43 of 100 dec 25, 2014 3.3 etherca t slave controller function (r - in32m3 - ec only) the ethercat slave controller (esc) core is made by beckhoff automation gmbh, germany . the esc processes ethercat communication s and acts as interface between ethercat field bus and slave application s . table 3 . 1 feature s of the ethercat slave controller feature r - in32m3 - ec et1100 remark ports 2 2 - 4 - fmmus 8 8 - syncmanagers 8 8 - ram [k b yte] 8 8 - distributed clocks 64bit 64bit - ebus no yes (0 - 4) - process d ata interfaces digital i/o no yes - spi slave no yes - external mp u interface cortex - m3 and 16bit/32bit async./sync. sram host interface 8bit/16bit async./sync. r - in32m3 does not support direct access to the esc from an external cpu. r - in32m3 series data sheet 3 . specifications r18ds0008ej0204 page 44 of 100 dec 25, 2014 3.4 cc- link ie field (intelligent device station) function (r - in32m3 - cl only) the outline specifications of cc - link ie field network are as follows. please refer to th e following url of cc- link partner association ( clpa ) for additional details and specification s for the cc- link ie field core. http://www.cc - link.org/jp/cclink/cclinkie/index.html table 3 . 2 cc- link ie field o utline s pecifications item specification ethernet standards ieee802.3ab (1000base - t) compliant communication speed 1gbps topology line, star, ring maximum number of connected units 254 modules (total of maste r and slave stations) maximum station - to - station distance 100m r - in32m3 series data sheet 3 . specifications r18ds0008ej0204 page 45 of 100 dec 25, 2014 3.5 general dma c ontroller 3.5.1 feature s - instances : 4 channel s (each channel is independent ) - transfer data size ? i ndependently selectable source and destination size ? s ize range : 8 - bit to 512 - bi t - max im um number of transfer byte s : 2 32 - 1 - channel priority control ? fixed p riority mode ? round robin mode - dma transfer method s ? register mode : dma transfer is performed using the values set in the control registers of the dma controller written by the c pu. t his mode supports conventional general dma transfer. ? link mode : dma transfer is performed according to a descriptor located in data ram and external memory. t he responsiveness of this mode is inferior to register mode because access of the descripto r occur s at every dma transfer. - skip function c ontinuous access size and discrete access size can each be set for the areas that are accessed with dma transfer. following access of the set size, it is possible to skip to the next address to be accessed. - intra - buffer data sweep function the data in the buffer can be output when the dmac is forcibly stopped. after sweeping, dma transfers continue sequentially . - suspend function e xecution of a dma transaction can be paused (suspended). - dma transfers inter val setting function the interval between dma transfers can be set in order to adjust the bus usage rate . - transfer mode ? single transfer mode when a dma transfer request is acknowledged, the dmac controls and then releases the bus once for each transfer. ad ditional dma requests are required for each subsequent transfer. ? block transfer mode when dma transfer request is acknowledged, the dmac takes control of the bus and repeats data transmission until completion of the number of transfers indicated bhy the co ntrol register. . but this mode does not occupy the bus . caution please align data at 512 - bit boundaries for 512 - bit transfer s . r - in32m3 series data sheet 3 . specifications r18ds0008ej0204 page 46 of 100 dec 25, 2014 3.6 dma c ontroller for real - time p ort 3.6.1 f eatures - instances : 1 channel - transfer data size ? i ndependently selectable source and d estination size ? s ize range : 8 - bit to 128 - bit - max imum number of transfer byte s : 2 32 - 1 - dma transfer method s ? register mode : dma tran sfer is performed using the values set in the control registers of the dma controller written by the cpu. t his mode suppo rts the conventional general dma transfer. ? link mode : dma transfer is performed according to a descriptor located in data ram and external memory. the responsiveness of this mode is inferior to register mode because the access of the descriptor occur s at every dma transfer. - skip function c ontinuous access size and discrete access size can each be set for the areas that are accessed with dma transfer. following access of the set size, it is possible to skip to the next address to be accessed. - intra - buff er data sweep function the data in the buffer can be output when the dmac is forcibly stopped. after sweeping, dma transfers continue sequentially . - suspend function e xecution of a dma transaction can be paused (suspended). - dma transfers interval setting function the interval between dma transfers can be set in order to adjust the bus usage rate . - transfer mode ? single transfer mode when a dma transfer request is acknowledged, the dmac controls and then releases the bus once for each transfer. additional d ma requests are required for each subsequent transfer. ? block transfer mode when dma transfer request is acknowledged, the dmac takes control of the bus and and repeats data transmission until completion of the number of transfers indicated by the control r egister. but this mode does not occupy the bus. caution please align data at 128 - bit boundaries for 128 - bit transfer. r - in32m3 series data sheet 3 . specifications r18ds0008ej0204 page 47 of 100 dec 25, 2014 3.7 watchdog timer 3.7.1 f eature s - con figuration af ter reset is based o n option settings - software trigger ed start mode - error mode option s ? generates nmi on error detection ? generates reset on error detection - window watchdog function - overflow interval time ? 25mh z operation : 163 s to 5.36 s r - in32m3 series data sheet 3 . specifications r18ds0008ej0204 page 48 of 100 dec 25, 2014 3.8 timer array unit 3.8.1 f eature s - 1 unit ( 4 channels ) - 32- bit counter and 32 - bit data register s per channel - independent channel operation - synchronous channel operation (master and slave operation) - generation of different types of output signal s - counter can be triggered by an external signal - interrupt generation independent channel operation synchronous ch annel operation independent channel operation functions synchronous channel operation function interval timer function pwm output function external input interval timer function independent channel signal measurement functions overflow interrupt ou tput function (during external width measurement) external input period count detection function external input pulse interval judgment function external input signal width judgment function other independent channel function external input posit ion detection function - supplement timers support prescaler options: selectable count clock from among four types of internal clocks as well as from an external clock. each timer may be configured to pclk frequency divided by 2 0 to 2 15 , and one clock may be configured to be divided by 1 to 256. r - in32m3 series data sheet 3 . specifications r18ds0008ej0204 page 49 of 100 dec 25, 2014 3.9 asynchronous serial interface 3.9.1 f eature s - full - duplex communication via built - in receive and transmit fifos ? internal 10 - bit x 16 receive data fifo ? internal 8 - bit x 16 transmit data fifo - 2 - pin configuration ? tra nsmit data output pin ? receive data input pin - e rror detection functions ? rx parity error ? rx framing error ? tx data consistency error - tx fifo overflow error ? rx fifo overrun error ? rx timeout error ? rx bf receive error - fifo status information ? rx fifo full/empt y status ? tx fifo empty/empty status ? rx fifo fill level ? tx fifo fill level - interrupt requests: 3 ? transmission interrupt ? reception interrupt ? status interrupt - character length: 7 or 8 - bits - par ity options : odd, even, 0, none - transmission stop bit s : 1 or 2 - bits - msb - /lsb - first transfer selectable - transmit/receive data inverted input/output option - 13 to 20 bits selectable for the bf (break field) in the lin (local interconnect network) communication format ? recognition of 11 bits or more possible for bf r eception in lin communication format ? bf reception flag provided - bf reception can be detected during data communication - bus monitor function to keep data consistency of the transmit data - supported baud rate: 300 to 12,500,000bps (tbd) r - in32m3 series data sheet 3 . specifications r18ds0008ej0204 page 50 of 100 dec 25, 2014 table 3 . 3 baud rate generator clocks output (pclk 100mhz) baud rate (bps) prescaler clock (prsclk) divisor ? urtjnprs? baud rate clock (brclk) divisor ? urtjnbrs? err ( %) 300 6 2604 0.01 600 5 2604 0.01 1200 4 2604 0.01 2400 3 2604 0.01 4 800 2 2604 0.01 9600 1 2604 0.01 19200 0 2604 0.01 31250 0 1600 0.01 38400 0 1302 0.01 76800 0 651 0.01 115200 0 434 0.01 153600 0 326 - 0.15 312500 0 160 0.00 1000000 0 50 0.00 2000000 0 25 0.00 2500000 0 20 0.00 5000000 0 10 0.00 6250000 0 8 0.00 1000000 0 5 0.00 1250000 0 4 0.00 r - in32m3 series data sheet 3 . specifications r18ds0008ej0204 page 51 of 100 dec 25, 2014 3.10 clocked serial interface 3.10.1 f eature s - three - wire serial synchronous data transfer - selectable m aster mode or slave mode - multiple slave configuration plus rcb (recessive configuration for broadcasting) thanks to two configurable chip select output signals (selectable chip selec priority) - built - in baud rate generator - adjustable baud rate; in slave mode it is determined by the input clock - maximum transmission speed: (at 100mhz pclk operation) ? in master mode: pclk/4 ? in slave mode: pclk/6 - phase of clock and data selectable - data transfer with msb or lsb first selectable - transfer data length selectable from 7 to 16 bits in 1 - bit increments - extended data length (edl) function for transferring more than 16 bits of data - three selectable transfer modes : ? transmission mode ? reception mode ? transmission/reception mode - error detection (data consistency check, parity, timeout, overflow, overrun) - full support of job concept - 128 words i/o buffer memory - memory mode selectable (fifo, dual buffer, tx - only buffer, direct access) - four different interrupt request signals ? communication interrupt ? reception interrupt ? error interrupt ? job completion interrupt - loop back mode (lbm) function for self - test r - in32m3 series data sheet 3 . specifications r18ds0008ej0204 page 52 of 100 dec 25, 2014 3.11 i2c bus 3.11.1 f eature s - operating mode ? standard mode (scl clock frequency: 100 khz max.) ? fast mode (scl clock frequency: 400 khz max.) - transfer mode ? single transfer mode ? continuous transfer mode - pin configuration ? serial clock pin ? serial transmit/receive data pin - interrupt request signal ? dat a transmit/receive interrupt request signal ? status interrupt request signal - communication data length ? 8 bits - multi master support ? multiple masters can control the bus simultaneously. - s erial clock signal level width ? s erial clock signal (scln) high - and l ow - level pulse width can be changed. - automatic detection ? s tart and stop conditions can be detected automatically r - in32m3 series data sheet 3 . specifications r18ds0008ej0204 page 53 of 100 dec 25, 2014 3.12 cc- link function the outline specifications of cc - link are as follows. please refer to the following url for the additional details of cc - li nk. http://www.cc - link.org/jp/cclink/index.html table 3 . 4 cc- link outline specifications item specification version ver1.10 and ver.2.00 kind of supported station intelligent device station (tbd), remote device station max. number of link points remote i/o : 8192 points each, remote re gister : 2048 words max. number of units connect 64 units communication speed and max. overall cable extension length 10mbps : 100m 5mbps : 160m 2.5mbps : 400m 625kbps : 900m 156kbps : 1200m communication system broadcast polling system caution to us e a remote device station, it is necessary to connect a ccs_refstb pin t o an external interrupt pin (intpz). r - in32m3 series data sheet 3 . specifications r18ds0008ej0204 page 54 of 100 dec 25, 2014 3.13 can controller 3.13.1 f eature s - compliant with iso - 11898 - standard frame and extended frame transmission/reception enabled - transfer rate: 1 mbps max. - 64 message buffers per channel - receive/transmit history list function (can be set individually for each message buffer) - automatic block transmission functio n - multi - buffer receive block function - mask setting of 8 patterns is possible for each channel, applicable for data and remote frames - data bit time, communication baud rate and sample point can be controlled ? for example : 66.7%, 70.0%, 75.0%, 80.0%, 81.3%, 85.0%, 87.5% ? baud rates in the range of 10 kbps up to 1 mbps can be configured - enhanced featu res : ? each message buffer can be configured to operate as a transmit or a receive message buffer ? a transmission request can be aborted by clearing the transmit - request flag of the relevant message buffer. supported by transmission abort interrupt, on succ essful abortion. ? automatic block transmission operation mode (abt) ? time stamp function in collaboration with timers capture channels ? a centralized global data update bit monitor register makes it possible to check all data update bits from one location r - in32m3 series data sheet 3 . specifications r18ds0008ej0204 page 55 of 100 dec 25, 2014 3.14 ex ternal mp u i nterface the e xternal m p u interface supports connect ion of an external mp u. note that the external m p u interface signal s are shared with the asynchronous sram memc and s ynchronous burst access memc ports. set memifsel to high to use these signa ls for an external mp u rather than for an external memory interface. when boot [ 0 - 1] is set to 1 ? b01, the device will boot from memory connected to csz0. please set memifsel pin level and hold it until after reset release ; dynamic switching of memifsel i s n o t supported. 3.14.1 f eature s (1) external m p u interface - interface direction ? sram (read, write) with wait output ? page rom (read) with wait output - s ynchronization - related ? hbusclk sync, async (set by hifsync pin) caution when you use asynchronous mode, please i nput low into a hbusclk pin. . - bus width ? 32- bit, 16 - bit (set by bus32en pin ) remark 8 bit bus width is n o t supported. - transfer data size ? 32- bit, 16 - bit, 8 - bit - buffer function ? write buffer : 1 step ? read buffer : max. 32 - byte prefetch supported - t ransfer type ? single transfer ? page read transfer - timing control function (2) ahb master port function - amba ver2.0 following ? 32- bit ahb - lite ? little endian fixed - address conversion ? accusable to 2mbyte area in ahb memor y area (4gbyte) from external mp u - bus si zing function ? external 16 - bit => 32 - bit - error response function ? output interrupt request (herroutz) in case of receiving error response ? stored the access information of the cause of error in the register r - in32m3 series data sheet 3 . specifications r18ds0008ej0204 page 56 of 100 dec 25, 2014 (3) status check function - check status of: ? internal reset ? hifsync pin and bus32en pin states r - in32m3 series data sheet 3 . specifications r18ds0008ej0204 page 57 of 100 dec 25, 2014 3.15 as ynchronous sram memc asynchronous sram memc can be conn ected to page rom, rom, sram or other peripheral device thar provides a 16 - or 32 - bit sram interface . asynchronous sram memc? s signal s are shared with the s ame ports used for s ynchronous burst access memc and the external m p u interface; please set memc sel and memifsel low to enable asynchronous sram memc mode. . when boot0 is low and boot1 is high , the device will boot from memory conne cted to csz0. 3.15.1 features - memory controller supporting page rom, rom, sram - 32- or 16 - bit data bus - static memory control function ? supports sram and peripheral device s with sram interface ? page rom support ( support ed stcsz0 only) ? f our chip select signal s are available ( stcsz0 - stcs z3 ) stcsz0 : page rom / sram : 1000 0000h - 13ff_ffffh (64mbyte) stcsz1 : sram only 1400 0000h - 17ff_ffffh (64mbyte) stcsz2 : sram only 1800 0000h - 1bff_ffffh (64mbyte) stcsz3 : sram only 1c00 0000h - 1fff_ffffh (64mbyte) - programmable wait function ? address setting wait ? data wait ? write recovery wait ? idle state r - in32m3 series data sheet 3 . specifications r18ds0008ej0204 page 58 of 100 dec 25, 2014 3.16 synchronous burst access memc the synchronous burst access memc can be connected to page rom, rom, sram, psram, nor - flash and other peripheral device s which provide a 16 - or 32 - bit sram interface . i t can also support multiplexed address/data signals when admuxmode pin is set high . sync hronous burst access me mc ?s signal s are shared with the same ports used for asynch ronous sram memc and external mp u interface; please set memcsel high and memifsel low to enable synchronous burst access memc mode . when boot0 is low and boot1 is high , the d evice will boot from memory connected to csz0. 3.16.1 feature s - memory controller supports page rom, rom, sram (sync or async), psram and nor - flash - 32- or 16 - bit data bus - address / data multiplex option remark page access is supported in async access mode onl y. - static memory control function ? sram (sync or async) and other peripheral device s which provide a 16 - or 32 - bit sram interface ? f our chip select signal s is available (csz0 - csz3) csz0 : 1000 0000h - 13ff_ffffh (64mbyte) csz1 : 1400 0000h - 17ff_ffffh (64mbyte) csz2 : 1800 0000h - 1bff_ffffh (64mbyte) csz3 : 1c00 0000h - 1fff_ffffh (64mbyte) remark each cs can be set between 1000_ 0000h - 1fff_ffffh by the programmable smadsel regist er . - programmable wait setting functions ? data wait ? write recovery wait ? idle state - m emory access frequency option (by dividing 100mhz signal by 2 to 6 ) - up to four wait state signal s avail able (waitz0 - waitz3) r - in32m3 series data sheet 3 . specifications r18ds0008ej0204 page 59 of 100 dec 25, 2014 3.17 instruction ram instruction ram is 768kb yte s of memory that can be accessed from i - code ahb , d - code ahb, dmac or an external mp u. 3.17.1 feature s - 128- bit (32 - bit x 4) read buffer - low latency : ? read latency : 2 (1 for accessing read buffer) ? write latency: 1 - 32- bit ahb bus - 128- bit ram data bus widt h (without ecc circuit) - selectable 16- or 32- bit transfer size - burst transmission: single, imprecise burst, precise burst (incr4/8/16, wrap4/8/16) - l ittle endian fixed 3.17.2 read buffer features - 128- bit (32bit x 4) read buffer - reply to ahb with 0 wait in ca se s of accessing read buffer - clear the data in the read buffer in case of 2 - bit ecc error - a 2 - bit ecc error at the time of the r ead response generates an ecc error interrupt and treats it as an error response of the ahb bus . 3.17.3 write interface features - 16- bit w rite access is supported; when two 16 - bit words are written to iram, they are automatically merged into a 32 - bit word in the ram. - error is generated on 8 - bit write attempts caution always ensure external host mp u writed 32 - bits at a time. r - in32m3 series data sheet 3 . specifications r18ds0008ej0204 page 60 of 100 dec 25, 2014 3.18 da ta ram data ram is 512kb yte s of memory that can be accessed from ahb and the ethernet accelerator ( header endec (encoder/decoder)) . 3.18.1 feature s - ahb latency: ? read / write latency 1 (latency 2 for read access after write access) - communication bus latency : 1 for read /write access - round - robin bus a rbitration - 32- bit ahb bus width - 128- bit communication b us width - 128- bit ram bus width (without ecc) - ahb transfer size : 8/16/ 32 - bit selectable - communication bus transfer size : 8/16/32/128 - bit selectable - bu rst transmission : single, imprecise burst, precise burst (incr4/8/16, wrap4/8/16) - l ittle endian fixed r - in32m3 series data sheet 3 . specifications r18ds0008ej0204 page 61 of 100 dec 25, 2014 3.19 buffer ram buffer ram is 64k b yte of memory that can be accessed by the ahb and communication busses . 3.19.1 feature s - communication bus latency : 1 for read / write access - fixed - priority communication bus arbitration - 128- bit communication bus width - 128- bit ram b us width (without ecc) - communication bus trans fer size: 8/16/32/128 - bit selectable r - in32m3 series data sheet 3 . specifications r18ds0008ej0204 page 62 of 100 dec 25, 2014 3.20 hardware real - time os the hardware real - time os supports 30 ty pes of system - call s including event , semaphore and mailbox . 3.20.1 feature s - task scheduler ? hardware isr : max imum 32 selectable from 128 qints ? context s : 64 ? semaphore s : 128 ? event s : 64 ? mailbox es : 64 ? mailbox elements : 92 ? c ontext priorit ies : 16 - hardware func tion manager r - in32m3 series data sheet 3 . specifications r18ds0008ej0204 page 63 of 100 dec 25, 2014 context cotrol register cntx type 0 [1:0 ] prty 0 [1:0] cntx_stat_0 [2:0] init_add_0 [31:0] wt_rsn_0 sm_id_0 [7:0] event_id_0 [7:0] event_flg_0 [15:0] flg_cnd_0 wt_timout _0 at_clr_0 rsdn_tim_0 hwfunc_id_0 cll_typ_0 rslt_rg_0 cntx type 0 [1:0] prty 0 [1:0] cntx_stat_n [2:0] init_add_n [ 31:0] wt_rsn_n sm_id_n [7:0] event_id_n [7:0] event_flg_n [15:0] flg_cnd_n wt_timout _n at_clr_n rsdn_tim_n hwfunc_id_n cll_typ_n rslt_rg_n contx_0 contx_n cortex ?-m3 ahb bus bridge select controller event table semaphor e table mail box scheduler hw function manager interrupt manager hw function hw function hw function hw function hw function rtos core qint [31:0] mt bus system call control signal gp bus i/f n = max 63 figure 3 . 1 structure of hardware real - time os r - in32m3 series data sheet 3 . specifications r18ds0008ej0204 page 64 of 100 dec 25, 2014 3.20.2 service call s ( 1/3 ) item name function hw - rtos driver itron ver. 4.0 standard profile task management functions act_t sk active task - iact_tsk active task - can_act cancel task activation r equest - sta_tsk active task (with a start code) - ext_tsk terminate and delete invoking task ter_tsk terminate task chg_pri c hange task priority get_ pri reference task priority task dependent synchronization function s slp_tsk put task to sleep tslp_tsk put task to sleep (with timeout) wup_tsk wakeup task iwup_tsk wakeup task can_wup cancel task wakeup request rel_wai release task from waiting i rel_wai release task from waiting sus_tsk suspend task - frsm_tsk forcibly resume suspended task - dly_tsk delay task - task exception handling function s ras_tex raise task exception handling - iras_tex raise task exception handling - dis_tex disable task exception - ena_tex enable task exception - sns_tex reference task exception handling state - synchronization and communication functions semaphore cre_sem create semaphore - del_sem delete semaphore - wai_sem acquire semaphore resource pol_sem acquire semaphore resource (polling) twai_sem acquire semaphore resource ( with timeout ) sig_sem release semaphore resource isig_sem release semaphore resource r - in32m3 series data sheet 3 . specifications r18ds0008ej0204 page 65 of 100 dec 25, 2014 ( 2/3 ) item name function h w - rtos driver itron ver. 4.0 standard profile synchronization and communication functions eventflag cre_flg create eventflag - del_flg delete eventflag - set_flg set eventflag iset_flg set eventflag clr_flg clear eventflag - wai_flg wait for eventflag pol_flg wait for eventflag (polling) twai_flg wait for eventflag ( with timeout ) d ata queue snd_dtq send to data queue - psnd_dtq send to data queue (polling) - ipsnd _dtq send to data queue (polling) - tsnd_dtq send to data queue (with timeout) - fsnd_dtq forced send to data queue - ifsnd_dtq forced send to data queue - rcv_dtq receive from data queue - prcv_dtq receive from data queue (polling ) - mailbox cre_mbx create mailbox - del_mbx delete mailbox - snd_mbx send to mailbox rcv_mbx receive from mailbox prcv_mbx receive from mailbox (polling) trcv_mbx receive from mailbox (with timeout) extended s ynchr onization and communication functions mutex cre_mtx create mutex - del_mtx delete mutex - loc_mtx lock mutex - ploc_mtx lock mutex (polling) - tloc_mtx lock mutex (with timeout) - unl_mtx unlock mutex - memory pool management fu nctions (fixed - sized) get_mpf acquire fixed - sized memory block - pget_mpf acquire fixed - sized memory block (polling) - tget_mpf acquire fixed - sized memory block (with timeout) - rel_mpf release variable - sized memory block - r - in32m3 series data sheet 3 . specifications r18ds0008ej0204 page 66 of 100 dec 25, 2014 ( 3/3 ) item name function h w - rtos driver itron ver. 4.0 standard profile time management functions set_tim set system time get_tim acquire system time isig_tim supply time tick - system state management functions rot_rdq rotate task precedence irot_r dq rotate task precedence get_tid acquire task id in the running state iget_tid reference task id in the running state loc_cpu lock the cpu iloc_cpu lock the cpu - unl_cpu unl ock the cpu iunl_cpu unlock the cpu - sns_l oc reference cpu state dis_dsp disable dispatching ena_dsp enable dispatching sns_dsp reference dispatching state - sns_dpn reference dispatching pending state - r - in32m3 series data sheet 3 . specifications r18ds0008ej0204 page 67 of 100 dec 25, 2014 3.21 port functions the ports rp0 - rp3 provide dedicated interface s t o the ahb bus separate from other ports and enables , allowing for real - time 32- bit data transmission. for each regi ster, grouping into 8 , 16 , or 32 bit - access is supported . 3.21.1 feature s - 96 i/o ports - shared with i/o port s of other peripheral circuit s - ports can be designated as i nput or output on a 1 - bit basis caution1. when changing the port mode control ( pmctn ) register s, shared s ignal s may generate spike noise . therefore, please take the following general spike noise counter measures via software: - c hange signal s only after stopping operation of the related internal peripheral circuit s - release the mask after clearing the i nterrupt request flag in port s shared with interrupt signal s - change mode after setting the output value. caution 2. please do n o t suppl y intermediate voltage from external sources because input buffer s are not protected against i nput th rough c urren t. make sure inputs are ? full - rail ? 0 or 1. 3.21.2 configuration there are 8 ports of 3 state i/o port and 4 ports controlling in real time built - in . i nput and output configuration is possible to 1 bit unit. the port is a basic 8 bits unit, but can read / write by the 32bit unit that aligned p0x - p3x, p4x - p7x, rp0x - rp3x . ( x = 0 to 7) in addition, real - time port (rp0x - rp3x) can input and output in sync with interrupt. for each register, grouping into 8, 16, or 32 bit - access is supported. r - in32m3 series data sheet 4 . electrical specifications r18ds0008ej0204 page 68 of 100 dec 25, 2014 4. electrical specifications 4.1 terminology table 4 . 1 terms used in absolute maximum ratings parameter symbol meaning power supply voltage v dd indicates the voltage range within which damage or reduced reliability will not result when power is applied to a vdd pin. input voltage v i indicates the voltage range within which damage or reduced reliability will not result when power is applied to an input pin. output voltage v o indicates the voltage range within which damage or reduced reliability will not result when power is applied to an output pin. output current i o indicates the absolute tolerance value for dc current to prevent damage or reduced reliability when a current flows out of or into an output pin. operating ambient temperature t a indicates the ambient temperature rang e for normal logic operations. storage temperature t stg indicates the element temperature range within which damage or reduced reliability will not result while no voltage or current is being applied to the device. table 4 . 2 terms used in recommended operating range ratings parameter symbol meaning power supply voltage v dd indicates the voltage range for normal logic operations that occur when vss = 0 v. input voltage, high v ih indicates the voltage, which is applied to the input pins of r - in32m3, is the voltage indicates that the high level state for normal operation of the input buffer. - if a voltage that is equal to or greater than the ?min.? value is applied, the input voltage is guaranteed as a high level v oltage. input voltage, low v il indicates the voltage, which is applied to the input pins of r - in32m3, is the voltage indicates that the low level state for normal operation of the input buffer. - if a voltage that is equal to or less than the ?max.? value i s applied, the input voltage is guaranteed as a low level voltage. positive trigger voltage v p indicates the input level at which the output level is inverted when the input to r - in32m3 is changed from the low - level side to the high - level side. negative trigger voltage v n indicates the input level at which the output level is inverted when the input to r - in32m3 is changed from the high - level side to the low - level side. hysteresis voltage v h indicates the differential between the positive trigger voltage and the negative trigger voltage. input rise time t rid , t ric , t ris indicates the limit value for the time period when an input voltage applied to r - in32m3 rises from 10% to 90%. trid, tric, and tris each indicate the input rise time for the data clock and schmitt buffer. input fall time t fid , t fic , t fis indicates the limit value for the time period when an input voltage applied to r - in32m3 falls from 90% to 10%. trid, tric, and tris each indicate the input fall time for the data clock and schmitt buffer. r - in32m3 series data sheet 4 . electrical specificat ions r18ds0008ej0204 page 69 of 100 dec 25, 2014 table 4 . 3 terms used for dc characteristics parameter symbol meaning static current consumption i dds indicates the current that flows from the power supply pins when the rated power supply voltage is being applied without any changes in t he input or output pin voltage. off - state output current i oz indicates the current that flows from the power supply pins when the rated power supply voltage is applied when a 3 - state output has high impedance. output short circuit current i os indicates t he current that flows when the output pins are shorted (to gnd pins) when output is at high level. input leakage current i li indicates the current that flows via an input pin when a voltage is applied to that pin. output current, low i ol indicates the cu rrent that flows to the output pins when the rated low - level output voltage is being applied. output current, high i oh indicates the current that flows from the output pins when the rated high - level output voltage is being applied. output voltage, low v o l indicates the output voltage at low level and when the output pin is open. output voltage, high v oh indicates the output voltage at high level and when the output pin is open. 4.2 solute maximum ratings table 4 . 4 absolute maximum ratings parameter symbol conditions ratings unit power supply voltage v dd 1.0v type - 0.5 to +1.4 v 3.3v type - 0.5 to +4.6 v i/o voltage v i /v o 3.3v buffer v i /v o < v dd + 0.5v - 0.5 to +4.6 v 5v - tolerant bu ffer v i /v o < v dd + 3.0 v - 0.5 to + 6.6 v output current (3.3v buffer) i o 6ma type 15 ma 12ma type 25 ma output current (5v - tolerant buffer) i o 4ma type 10.35 ma operating ambient temperature t a - - 40 to + 85 c storage temperature t stg - - 65 to + 125 c caution pr oduct quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore t he product must be used under conditions that ensure that the absolute maximum ratings are n ot exceeded. remark 3.3 v must be applied to the i/o pins only after applying the power supply voltage. r - in32m3 series data sheet 4 . electrical specifications r18ds0008ej0204 page 70 of 100 dec 25, 2014 4.3 recommended operating conditions table 4 . 5 recommended operating conditions parameter symbol conditions min. typ. max. unit power supply voltage v dd 1 . 0 v power supply 0.9 1.0 1.1 v 3.3v power supply 3.0 3.3 3.6 v negative trigger voltage v n 3.3v buffer 0.6 - 1.8 v 5v - tolerant buffer 0.8 - 1.1 v positive trigger voltage v p 3.3v buffer 1.2 - 2.4 v 5v - tolerant buffer 1.7 - 2.2 v hysteresis voltage v h 3.3v buffer 0.3 - 1.5 v 5v - tolerant buffer 0.9 - 1.1 v input voltage, low v il 3.3 v buffer - 0.3 - 0.8 v 5v - tole rant buffer 0 - 0.8 v input voltage, high v ih 3.3 v buffer 2.0 - v dd + 0.3 v 5v - tolerant buffer 2.0 - 5.5 v input rise/fall time t r id - 0 - 200 ns t f id - 0 - 200 ns input rise/fall time (clock) t ric - 0 - 4 ns t f ic - 0 - 4 ns input rise/fall time (schmitt input) t ris - 0 - 1 ms t fis - 0 - 1 ms operating ambient temperature t a - -40 - 85 c r - in32m3 series data sheet 4 . electrical specifications r18ds0008ej0204 page 71 of 100 dec 25, 2014 4.4 dc characteristics table 4 . 6 dc characteristics (vdd = 3.3 0.3 v, ta = ? 40 to +85 c) (1/2) parameter symbol c onditions min. typ. max. unit supply current (r - in32m 3 - ec) i dd v i = v dd or gnd internal regulator using - - - 1.0v - 270 880 ma 3.3v - 210 220 ma internal regulator not using - 1.0v 270 880 ma 3.3v 120 130 ma 1.5v - 150 170 ma supply current (r - in32m3 - cl ) i dd v i = v dd or gnd 1.0v - 280 890 ma 3.3v - 45 50 ma off - state current i oz v i = v dd or gnd 3.3v output - - 10 a 5v - tolerant buffer - - 10 a output short circuit current note i os v o = gnd - - - -250 ma input leakage current (3.3v buffer) i i v i = v dd or gnd normal input - - 10 a v i = gnd w ith pull - up re s ist o r (5k ) - 293.8 - 645.7 - 1181.3 a with pul l - up res ist o r (5 0 k) - 28.9 - 65.7 - 129.8 a v i = v dd with pull - down resistor (50k) 10.2 43.4 83.9 a input leakage current (5v - tolerant buffer) i i v i = gnd with pull - down resistor (50k) 39.0 - 100.9 a note the output short circuit time is no more than one second and is only for one pin on the lsi. remark in the notes for the table, the (+) and ( ? ) signs indicate the current direction. current flowing to the device is indicated by (+) and current flowing out is indicated by ( ? ). table 4 . 7 dc characteristics (vdd = 3.3 0.3 v, ta = ? 40 to +85 o c) ( 2 /2) parameter symbol conditions min. typ. max. unit output current, low i ol v ol = 0.4v 6 ma type 6.0 - - ma (3.3v buffer) 12 ma type 12.0 - - ma output current, low (5v - tolerant buffer) i ol v ol = 0.4v 4ma type 4.0 - - ma output current, high i o h v oh = 2.4v 6 ma type - 6.0 - - ma (3.3v buffer) 12 ma type - 12.0 - - ma output current, high (5v - tolerant buffer) i o h v oh = 2.4v 4ma type - 4.0 - - ma output voltage, low v ol i ol = 0ma 3.3v buffer - - 0.1 v 5v - tolerant buffer - - 0.1 v output voltage, high v oh i ol = 0ma 3.3v buffer vdd - 0.1 - - v 5v - tolerant buffer vdd - 0.1 - - v r - in32m3 series data sheet 4 . electrical specifications r18ds0008ej0204 page 72 of 100 dec 25, 2014 4.5 pull - up/pull - down resistor values table 4 . 8 pull - up/pull - down resistor values (vdd = 3.3 0.3 v, ta = ? 40 to +85 o c) parameter library specification min. typ. max. unit pull - up resistor (3.3v buffer) 50k 27.7 50.2 103.9 k pull - up resistor (5v - tolerant buffer) 50k 35. 7 51.2 77.0 k pull - down resistor (3.3v buffer) 50k 42.9 76.1 295.5 k r - in32m3 series data sheet 4 . electrical specifications r18ds0008ej0204 page 73 of 100 dec 25, 2014 4.6 power - on/off sequence power structure of the r - in32m3 series is internal power (vdd10 : 1.0v) and i/o power (vdd33 : 3.3v) and phy power supply (vdd15 : 1.5v) . (phy power is subj ect only r - in32m3 - ec.) power is recommended to put the i/o power (vdd33 : 3.3v) after switching on the internal power supply (vdd10 : 1.0v). in addition, power - off is recommend internal power - off(vdd1 : 1.0v) after cut - off of i/o power(vdd33 : 3.3v). i n the case of supplying internal power after i/o power, please note that i/o value becomes an indefinite due to uncertain mode while i/o is powered on but internal power isn ? t , regardless of an input( output ) mode. also, 3.3 v must be applied to the i/o pins only after applying the power supply voltage s . power on/off time difference, that regardless of the power - on sequence, i t does not matter which power supply is applied to (or removed from) the device first (vdd1/ivdd or vdd3/evdd), but it is recommen ded to ensure 100ms or less time difference between the application or removal of each power supply. the 100ms or less time measurement is based on the period from 10% to 90% of each voltage range. i/o voltage vdd 33 100ms 0 .1 vdd 10 gnd internal voltage vdd 10 100ms 0 .1 vdd 10 0 .9 vdd 33 phy voltage note vdd15 figure 4 . 1 recommended sequence of power - on/off note the timing for phy power supply voltage vdd15 only needs to be observed, when the internal regulator in the r - in32m3 - ec device is not used. r - in32m3 series data sheet 4 . electrical specifications r18ds0008ej0204 page 74 of 100 dec 25, 2014 4.7 ac characteristics 4.7.1 clock signals (1) input clock characteristics parameter symbol conditions min max unit xt1, xt2 t sysclk - 25 50ppm mhz eth0_txc, eth1_txc t txc - - 25 mhz eth0_rxc, eth1_rxc t rxc - - 125 mhz ccm_ clk80m t cclclk - 80 50ppm mhz clk2_097m t cclieclk - 2.097 100ppm mhz hbusclk t hbusclk - - 50 mhz csisck0, csisck1 t csissck slave mode - 16.6 mhz tck t tck - - 50. mhz (2) output clock characteristics parameter symbol conditions min max unit busclk output cycle t busclk c l = 15pf 10 - ns busclk high level width t bckh 0.5 t busclk - 2.0 0.5 t busclk + 2.0 ns busclk low level width t bckl 0.5 t busclk - 2.0 0.5 t busclk + 2.0 ns busclk rise time t bckr - 1.2 ns busclk fall time t bckf - 1.2 ns clkout25m output cycle t co25m c l = 15pf 40 - ns clkout25m high level width t co25mh 0.5 t busclk - 5.3 0.5 t busclk + 5.3 ns clkout25m low level width t co25ml 0.5 t busclk - 5.3 0.5 t busclk + 5.3 ns clkout25m rise time t co25mr - 3.4 ns clkout25m fall time t co25mf - 3.4 ns etc_gtxc output frequency t gtxc c l = 13pf - 125 mhz c sisck output frequency t csimsck master mode c l = 15pf - 25 mhz scl output frequency t scl high speed mode c l = 30pf - 400 khz smsck output frequency t smsck c l = 15pf - 50 mhz cati2cclk output frequency t eciicclk c l = 30pf - 148.8 khz traceclk output fr equency t traceclk c l = 15pf - 50 mhz r - in32m3 series data sheet 4 . electrical specifications r18ds0008ej0204 page 75 of 100 dec 25, 2014 < t busclk > busclk ( output ) < t bckh > < t bckl > < t bckr > < t bckf > < t co 25 m > < t co 25 mh > < t co 25 ml > < t co 25 mr > < t co 25 mf > clkout 25 m ( output ) ? refer to each chapter for other clocks figure 4 . 2 output clock timing diagram r - in32m3 series data sheet 4 . electrical specifications r18ds0008ej0204 page 76 of 100 dec 25, 2014 4.7.2 reset signals parameter symbol conditions min max unit resetz low level width t wrsl - t he time required for the time (until the external oscillator be stab le + 1usec) r - in32m3 series data sheet 4 . electrical specifications r18ds0008ej0204 page 77 of 100 dec 25, 2014 4.7.3 external memory interface signals (1) d elay value calcula tion method the transition delay of the external memory interface pins depend on the capacirtive load driven, including both load input pins and substrate / pcb capacitance. t he table below shows how to calculate the delay based on capacitive load. drive capability delay value per pf ( ns ) min. max. 6ma 0.026 0.067 12ma 0.012 0.034 example when an address pin (6 - ma output buffer) has 30 - pf load, the actual delay is as follows. min. 1.0ns( the min delay value at the time of 0 pf ) + ( 0.026 30 ) ns = 1.78ns max. 7.0ns( the max delay value at the time of 0 pf ) + (0.067 30) ns = 9.01ns (2) asynch ronous sram memc access timing parameter symbol min max unit address, csz0 - csz3 output delay time t dka 1.0 (1.78) note 7.0 (9.01) note ns rdz output delay time t dkrd 1.0 (1.78) note 7.0 (9.01) note ns wrz0 - wrz3 (benz0 - benz3), wrstbz output delay time t dkwr 1.0 (1.78) note 7.0 (9.01) note ns bcystz output delay time t dkbsl 1.0 (1.78) note 7.0 (9.01) note ns waitz input setup time t skw 4.0 - ns waitz input hold time t hkw 0 - ns date input setup time t skid 4.0 - ns data input hold time t hkid 0 - ns date output delay time t dkod 1.0 (1.78) note 7.0 (9.01) note ns data float delay time t hkod 1.0 (1.78) note 7.0 (9.01) note ns note . values in parenthesis are based on a 30pf capacitive load. r - in32m3 series data sheet 4 . electrical specifications r18ds0008ej0204 page 78 of 100 dec 25, 2014 (a) read timing busclk ( output ) a 1 - a 26 ( output ) csz 0 - csz 3 ( output ) wrz 0 - wrz 3 note , wrstb ( output ) rdz ( output ) d 0 - d 31 ( i / o ) waitz ( input ) bcystz ( input ) < t dka > < t dka > < t dka > < t dkwr > < t dkwr > < t dkrd > < t dkrd > < t hkod > < t skid > < t hkid > < t skw > < t hkw > bez 0 - bez 3 note ( output ) < t dkbs > < t dkbs > figure 4 . 4 memory controller read timing diagram ( asynchronous memory ) note . wrz0 - wrz3 and benz0 - benz3 serve a dual purpose s; the function is selected by the wren register s . remark . t he timing diagram in figure 4.4 shows the case for wh en ?idle wait?, ?write recovery wait?,, and ?address wait? are set to 0, and ?data wait? is set to 3 . r - in32m3 series data sheet 4 . electrical specifications r18ds0008ej0204 page 79 of 100 dec 25, 2014 (b) write timing busclk ( output ) a 1 - a 26 ( output ) csz 0 - csz 3 ( output ) wrz 0 - wrz 3 note , wrstb ( output ) bez 0 - bez 3 note ( output ) rdz ( output ) d 0 - d 31 ( i / o ) waitz ( input ) bcystz ( input ) < t dka > < t dka > < t dka > < t dkwr > < t dkwr > < t hkod > < t dkod > < t dkod > < t skw > < t hkw > < t dkwr > < t dkwr > < t dkbs > < t dkbs > figure 4 . 5 memory controller read timing diagram ( asynchronous me mory ) note . wrz0 - wrz3 and benz0 - benz3 serve dual purpose s; the function is selected b y the wren register s . remark . the timing diagram in figure 4.4 shows the case for when ?idle wait?, ?write recovery wait?,, and ?address wait? are set to 0, and ?da ta wait? is set to 3 . r - in32m3 series data sheet 4 . electrical specifications r18ds0008ej0204 page 80 of 100 dec 25, 2014 (3) synchronous burst access memc access timing parameter symbol min max unit busclk output frequency t busclk - 50 mhz address csz0 - csz3 output delay time t dka 1.0 (1.78) note 7.8 (9.81) note ns rdz output delay time t dkrd 1.0 (1.78) note 7.8 (9.81) note ns wrz0 - wrz3 (benz0 - benz3), wrstbz output delay time t dkwr 1.0 (1.78) note 7.8 (9.81) note ns advz output delay tim e t dkbsl 1.0 (1.78) note 7.8 (9.81) note ns waitz input setup time t skw 5.3 - ns waitz input hold time t hkw 0 - ns data input setup time t skid 5.3 - ns data input hold time t hkid 0 - ns data output delay time t dkod 1.0 (1.78) note 7.8 (9.81) note ns data float delay time t hkod 1.0 (1.78) note 7.8 (9.81) note ns note . values in parenthesis are based on a 30pf capacitive load. r - in32m3 series data sheet 4 . electrical specifications r18ds0008ej0204 page 81 of 100 dec 25, 2014 (a) read timing busclk output ( smcmd _ cmcrdlth : 0 ) csz 0 - csz 3 output wrstbz output rdz output d 0 - d 31 i / o wait z input advz input < t dka > < t dka > < t d krd > < t d krd > < t hkod > < t sk id > < t hkid > < t sk w > < t hkw > < t d kbs > < t d kbs > busclk ( output ) ( smcmd _ cmcrdlth : 1 ) figure 4 . 6 memory controller read timing diagram ( synchronous memory ) remark . above timing is for the case where ?t_ceoe? is 2 and ?t_rc? is 4. r - in32m3 series data sheet 4 . electrical specifications r18ds0008ej0204 page 82 of 100 dec 25, 2014 (b) write timing busclk ( output ) csz 0 - csz 3 ( output ) wrstbz ( output ) rdz ( output ) d 0 - d 15 ( i / o ) waitz ( input ) advz ( input ) < t dka > < t dka > < t dkwr > < t dkwr > < t hkod > < t skid > < t dkod > < t skw > < t hkw > < t dkbs > < t dkbs > figure 4 . 7 memory controller write timing diagram ( synchronous memory) remark . above timing is for the case where ?t_ceoe? is 2 and ?t_rc? is 4. r - in32m3 series data sheet 4 . electrical specifications r18ds0008ej0204 page 83 of 100 dec 25, 2014 4.7.4 external microcomputer interface signal (1) s ynchronous mode parameter symbol min max unit address, hcsz/hpgcsz input setup time t skha 4.0 ns address, hcsz/hpgcsz input hold time t hkha 1.0 ns hrdz input setup time t shrd 4.0 ns hrdz input hold time t hhrd 1.0 ns hbenz0 - hbenz3 (hwrz0 - hwrz3), hwrstbz input setup time t skhwr 4.0 ns hbenz0 - hbenz3 (hwrz0 - hwrz3), hwrstbz input hold tim e t hkhwr 1.0 ns hbcystz input setup time t skhbs 4.0 ns hbcystz input hold time t hkhbs 1.0 ns waitz output delay time t dkhw 2.0 10.0 ns data input setup time t skihd 4.0 ns data input hold time t hkihd 1.0 ns data output delay time t dkohd 2.0 10.0 ns data float delay time t hkohd 2.0 10.0 ns hbusclk input cycle t hbusclk 20 ns hbusclk high level width t hbhigh 0.5t hbcyc - 2.1 0.5t hbcyc + 2.1 ns hbusclk low level width t hblow 0.5t hbcyc - 2.1 0.5t hbcyc + 2.1 ns r - in32m3 series data sheet 4 . electrical specifications r18ds0008ej0204 page 84 of 100 dec 25, 2014 (a) read timing hbusclk? input? ha1-ha20? input? hcsz, hpgcsz ? input? hwrz0 - hwrz3 ? , hwrstbz ? input? hrdz? input? hd0-hd31? output? hwaitz? otuput? hbcystz? input? < t hkha > < t dkohd > < t hkohd > hbez0 - hbez3 note ? input? < t skhbs > < t hkhbs > < t skha > < t skha > < t hkah > < t srd > < t hrd > < t hbusclk > < t hbhigh > < t hblow > < t srd > figure 4 . 8 external microcomputer interface read timing (synchronous mode) note hwrz0 - hwrz3 and hbenz0 - hbenz3 are made to serve a double purpose . it is decided which function will be used by the lev el which a hwrzsel pin inputs. r - in32m3 series data sheet 4 . electrical specifications r18ds0008ej0204 page 85 of 100 dec 25, 2014 (b) write timing hbusclk? input? ha1-ha20? input? hcsz, hpgcsz ? input? hrdz? input? hwrz0 - hwrz3 ? , hwrstbz ? input? hd0-hd31? input? hwaitz? output? hbcystz? input? < t hkha > < t skihd > < t hkihd > hbez0 - hbez3 note ? input? < t skhbs > < t hkhbs > < t skha > < t skha > < t hkah > < t hbusclk > < t hbhigh > < t hblow > < t skhwr > < t skhwr > < t hkhwrd > < t hkhwr > figure 4 . 9 external microcomputer interface write timing (synchronous mode) note hwrz0 - hwrz3 and hbenz0 - hbenz3 are made to serve a doub le purpose . it is decided which function will be used by the level which a hwrzsel pin inputs. r - in32m3 series data sheet 4 . electr ical specifications r18ds0008ej0204 page 86 of 100 dec 25, 2014 (2) asynchronous mode r - in32m3 series data sheet 4 . electrical specifications r18ds0008ej0204 page 87 of 100 dec 25, 2014 (a) read timing ha1-ha20input hcsz , hpgcszinput hwrz0 - hwrz3 note , hwrstbzinput hrdzinput hd0-hd31in/out hwaitzoutput < t rdhz > hbez0 - hbez3 note input < t skha > < t rdlz > hi-z < t rdwaitf > < t waitr > < t clz > figure 4 . 10 external microcomputer interface read timing ( a synchronous mode) note hwrz0 - hwrz3 and hbenz0 - hbenz3 are made to serve a double purpose . it is decided which function will be used by the level which a hwrzsel pin inputs. r - in32m3 series data sheet 4 . electrical specifications r18ds0008ej0204 page 88 of 100 dec 25, 2014 (b) writ e timing ha 1 - ha 20 input hcsz , hpgcsz input hrdz input hwrz 0 - hwrz 3 note , hwrstbz input hd 0 - hd 31 in / out hwaitz output < t chz > hbez 0 - hbez 3 note input hi - z < t wrwaitf > < t clz > < t wrs > figure 4 . 11 external microcomputer interface write timing ( a synchronous mode) note hwrz0 - hwrz3 and hbenz0 - hbenz3 are made to serve a double purpose . it is decided which fun ction will be used by the level which a hwrzsel pin inputs. r - in32m3 series data sheet 4 . electrical specifications r18ds0008ej0204 page 89 of 100 dec 25, 2014 4.7.5 serial flash rom interface parameter symbol conditions min max unit smsck output cycle t sfrcyc c l = 15pf 20 - ns smsck high level width t smckh 0.5 t sfrcyc - 2.0 0.5 t sfrcyc + 2.0 ns smsc k low level width t smckl 0.5 t sfrcyc - 2.0 0.5 t sfrcyc + 2.0 ns smsck rise time t smckr 1.9 ns smsck fall time t sfrcyc 1.9 ns smsck output delay time t dsmcsck c l = 15pf freq = 50mhz 7.5 note ns smcsz output delay time t dsmckcs c l = 15pf freq = 50mhz 11.5 note ns smcsz high level width t smcsh c l = 15pf 14 note ns smsi input setup time t ssmi - 6.0 - n s smsi input hold time t hsmi - 0 - ns smsi output delay time t dsmi c l = 15pf - 1.0 5.0 ns smso input setup time t ssmo - 6.0 - ns smso input hold time t hsmo - 0 - ns smso output delay time t dsmo c l = 15pf - 1.0 5.0 ns note timing can be extended by setting of sfmssc registor. p lease refer to 12.2.2 chip selection control register (sfmssc) of user?s manual (peripherals function) smsckoutput [spi mode 3] msb smsck output [ spi mode 0 ] sm csz output sm s o / smsi output sm s i / smso input figure 4 . 12 serial flash rom access timing diagram r - in32m3 series data sheet 4 . electrical specifications r18ds0008ej0204 page 90 of 100 dec 25, 2014 4.7.6 external dma interface parameter symbol conditions min max unit dmareqz [1:0], rtdmareqz input setup time t skdr - 7.0 - ns dmareqz [1:0], rtdmareqz input hold time 1 t hkdr1 - until dma ackz rtdmaackz - ns dmareqz [1:0], redmareqz input hold time 2 t hkdr2 - - t busclk note1 m note2 - 7.0 ns dmaackz [1:0], rtdmackz output delay time t dkda c l = 30pf 2.0 10.0 ns dmaackz [1:0], rtdmaackz output high level width t wdah - t busclk note1 m note2 - 8 t busclk note1 m note2 + 8 ns dmatcz [1:0], rtdmatcz output delay time t dktc c l = 30pf 2.0 10.0 ns note1 . t busclk is one cycle (10 ns) of busclk. note2 . m = 1 - 31 ( dmaifc0 , dmaifc 1, rtmdaifc registers). busclk ( output ) dmareqzn , rtdmareqz ( input ) dmaackzn , rtdmaackz ( output ) dmatczn , rtdmatcz ( output ) < t skdr > < t hkdr 1 > < t dkda > < t wdah > < t dktc > < t hkdr 2 > remark : n = 0 , 1 figu re 4 . 13 external dma access timing diagram r - in32m3 series data sheet 4 . electrical specifications r18ds0008ej0204 page 91 of 100 dec 25, 2014 4.7.7 csi interface the clocked serial interface (csi) supports both master and slave mode. (1) master mode parameter symbol conditions min max unit csisckn output cycle t csimsck c l = 15pf 40 - ns c sisin input setup time (csisckn posedge) t smsi - 8.5 - ns csisin input setup time (csisckn negedge) t smsi - 8.5 - ns csisin input hold time (csisckn posedge) t hmsi - 7.0 - ns csisin input hold time (csisckn negedge) t hmsi - 7.0 - ns csison output delay time (csisckn posedge) t dmso c l = 15pf - 7.0 ns csison output delay time (csisckn negedge) t dmso - 7.0 ns csison output hold time (csisckn posedge) t hmso t csimsck 0.5 - 5.0 - ns csison output hold time (csisckn negedge) t hmso t csimsck 0.5 - 5.0 - ns csisckn ( i / o ) csisin ( input ) remark : n = 0 , 1 csison ( output ) < t hmsi > < t csimsck > < t hmso > < t dmso > < t smsi > figure 4 . 14 csi access timing diagram (master mode) r - in32m3 series data sheet 4 . electrical specifications r18ds0008ej0204 page 92 of 100 dec 25, 2014 (2) slave mode parameter symbol conditions min max unit csisckn input cycle t csissck - 60 - ns csisin input setup time (c sisckn posedge) t sssi - 10.0 - ns csisin input setup time (csisckn negedge) t sssi - 10.0 - ns csisin input hold time (csisckn posedge) t hssi - 15 - ns csisin input hold time (csisckn negedge) t hssi - 15 - ns csison output delay time (csisckn posedge) t dsso c l = 15pf - 10.0 ns csison output delay time (csisckn negedge) t dsso - 10.0 ns csison output hold time (csisckn posedge) t hsso t csissck 0.5 - 5.0 - ns csison output hold time (csisckn negedge) t hsso t csissck 0.5 - 5.0 - ns csisckn ( i / o ) csisin ( input ) < t sssi > remark : n = 0 , 1 csison ( output ) < t hssi > < t csissck > < t hsso > < t dsso > figure 4 . 15 csi access timing diagram (slave mode) r - in32m3 series data sheet 4 . electrical specifications r18ds0008ej0204 page 93 of 100 dec 25, 2014 4.7.8 i2c interface parameter symbol conditions normal mode high speed mode unit min max min max scl clock frequency t scl c l = 30pf 0 100 0 400 khz bus - free time between the stop condition and start condition t buf 4.7 - 1.3 - s hold time t hsta 4.0 - 0.6 - s scl clock low - level width t scll 4.7 - 1.3 - s scl clock high - level width t sclh 4.0 - 0.6 - s setup time for the start and restart conditions t ssta 4.7 - 0.6 - s data hold time for a cbus compatible master t hdat 5.0 - - - s for an iic bus 0 - 0 0.9 s data setup time t sdat 250 - 100 - ns sda and scl signal rise time t sclr - 1000 20 + 0.1c b 300 ns sda and scl signal fall time t sclf - 300 20 + 0.1c b 300 ns stop condition setup time t ssto 4.0 - 0.6 - s pules width of spike suppressed by input filter t sp - - 0 50 ns capacitance load of each bus line c b - - 400 - 400 pf scln ( i / o ) remark : n = 0 , 1 . the statement of t sclr , and t sclf is omitted . sdan ( output ) stop condition start condition restart condition < t buf > < t hdat > < t sdat > < t ssta > < t hsta > < t sp > < t ssto > < t hsta > < t scl > < t scll > < t sclh > stop condition figure 4 . 16 i2c access timing diagram r - in32m3 series data sheet 4 . electrical specifications r18ds0008ej0204 page 94 of 100 dec 25, 2014 4.7.9 can interface parameter symbol conditions min max unit internal delay time t node c l = 30pf - 75 ns can internal clock ( i / o ) remark : n = 0 , 1 ctxdn ( transmission data ) < t output > < t input > crxdn ( reception data ) figure 4 . 17 can access timing diagram remark . can internal clock (f can ) can baud late clock internal delay time (t node ) = internal transmission delay time (t output ) + internal reception delay time (t input ) r - in 32 m 3 remark : n = 0 , 1 can controller internal transmission delay time < t output > internal recepstion delay time < t input > ctxdn pin crxdn pin figure 4 . 18 can access timing ( supplement ) r - in32m3 series data sheet 4 . electrical specifications r18ds0008ej0204 page 95 of 100 dec 25, 2014 4.7.10 ethernet interface (1) gmii interface parameter symbol conditions min max unit ethn_gtxc output cycle t gtxc c l = 13pf 8 - ns ethn_rxc input cycle t grxc - 8 - ns ethn_txdm output delay time t dgtkt d c l = 13pf 0.5 5 .5 ns ethn_txen, ethn_txer output delay time t dgtkte c l = 13pf 0.5 5 .5 ns ethn_rxd input setup time t sgrdrk - 2.0 - ns ethn_rxd input hold time t hgrdrk - 0 - ns ethn_rxdv, ethn_rxer input setup time t sgrvrk - 2.0 - ns ethn_rxdv, ethn_ rxer input hold time t hgrvrk - 0 - ns remark . n = 0, 1, m = 0 - 7 . ethn _ gtxc ( output ) remark : n = 0 , 1 ethn _ txd [ 7 : 0 ] ( output ) ethn _ txen ethn _ txer ( output ) < t dgtktd > < t dgtkte > < t dgtkte > < t gtxc > figure 4 . 19 ethernet access timing diagram (gmii transmission ) ethn _ rxc ( input ) remark : n = 0 , 1 ethn _ rxd [ 7 : 0 ] ( input ) ethn _ rxdv ethn _ rxer ( input ) < t sgrdrk > < t hgrvrk > < t sgrvrk > < t hgrdrk > < t grxc > figure 4 . 20 ethernet access timing diagram (gmii reception) r - in32m3 series data sheet 4 . electrical specifications r18ds0008ej0204 page 96 of 100 dec 25, 2014 (2) mii interface parameter symbol condition s min max unit ethn_txc input cycle t txc - 40 - ns ethn_rxc input cycle t rxc - 40 - ns ethn_txdm output delay time t dtktd c l = 30pf 0 25 ns ethn_txen, ethn_txer output delay time t dtkte c l = 30pf 0 25 ns ethn_rxd input setup time t srdrk - 10 - ns eth n_rxd input hold time t hrdrk - 10 - ns ethn_rxdv, ethn_rxer input setup time t srvrk - 10 - ns ethn_rxdv, ethn_rxer input hold time t hrvrk - 10 - ns remark . n = 0, 1, m = 0 - 7 . ethn _ txc ( input ) remark : n = 0 , 1 ethn _ txd [ 7 : 0 ] ( output ) ethn _ txen ethn _ txer ( oiutput ) < t dtktd > < t dtkte > < t dtkte > < t txc > figure 4 . 21 ethernet access timing diagram (mii transmission) ethn _ rxc ( input ) remark : n = 0 , 1 ethn _ rxd [ 7 : 0 ] ( input ) ethn _ rxdv ethn _ rxer ( input ) < t srdrk > < t hrvrk > < t srvrk > < t hrdrk > < t rxc > figure 4 . 22 ethernet access timing (mii reception) r - in32m3 series data sheet 4 . electrical specifications r18ds0008ej0204 page 97 of 100 dec 25, 2014 (3) serial management interface parameter symbol condi tions min max unit eth_mdc output cycle t mdc c l = 30pf 80 - ns eth_mdio input setup time t smdio 10 - ns eth_mdio input hold time t hmdio 0 - ns eth_mdio output delay time t dmdio 20 - ns eth _ mdc ( output ) eth _ mdio ( input ) < t mdc > < t hmdio > eth _ mdio ( output ) < t dmdio > < t dmdio > < t smdio > figure 4 . 23 ethernet access timing diagram (serial management) r - in32m3 series data sheet 4 . electrical specifications r18ds0008ej0204 page 98 of 100 dec 25, 2014 4.7.11 debug interface (1) debug serial interface parameter symbol conditions min max unit tck input cycle t tck - 20 - ns tms input setup time t stms - 6.5 - ns tms input hold time t htms - 0 - ns tdi input setup time t stdi - 6.5 - ns tdi input hold time t htdi - 0 - ns tdo output delay time t dtdo c l = 30pf 3.0 13.0 ns tck ( input ) tms ( input ) tdi ( input ) tdo ( output ) < t stdi > < t stms > < t htms > < t htdi > < t dtdo > < t tck > figure 4 . 24 debug serial interface r - in32m3 series data sheet 4 . electrical specifications r18ds0008ej0204 page 99 of 100 dec 25, 2014 (2) trace in terface parameter symbol conditions min max unit traceclk output frequency t trcclk c l = 15pf 20 - ns tracedata output delay time t dtrcdat c l = 15pf 0.26 3.43 ns tracedata 0 - tracedata 3 ( output ) < t dtrcdat > traceclk ( output ) < t dtrcdat > < t trcclk > figure 4 . 25 trac e interface r - in32m3 series data sheet 5 . package drawing r18ds0008ej0204 page 100 of 100 dec 25, 2014 5. package drawing r - in32m3 series data sheet revision history c -1 revision history r - in32m3 series data sheet rev. date description page summary preliminary 1.00 2011.06.14 - first edition issued preliminary 2.00 2012.12.03 overall change the description of ?cc - link ie field? ? cc - link ie field network ? ? cc - link ie field ? 12-13 addition of 2.1 pin placement 14-16 modification of 2.3.1 ethernet signal 20 modification of pin name of 2.3.5 port signal, real - time port signal 26 modification of l evel during reset of 2.3.9 timer i/o signal 28 a ddition of new pin information of 2.3.14 system signal 29 addition of new pin information of 2.3.15 test signal 30 addition of new pin information of 2.3.16 operation mode setting signal 36 addition of new pin information of 2.4.4test signal 39-62 addition of 3 specification 65-68 modification of the description of output buffer of 4 electrical specifications 69 addition of 4.6 power - on/off sequence 70-8 9 addition of 4.7 ac characteristics preliminary 2013.1.17 2 modification of acce ss to external memory of 1.3 overview 3.00 3 modification of status of cc - link of 1.3 overview addition etherphy information of 1.3 overview 4 modification of block diagram of r - in32m3- ec of 1.4 internal block diagram 5 modification of block diagra m of r - in32m3- cl of 1.4 internal block diagram 14 modification of list of phy interface of 2.3. 1 ethernet signal 16 modification of l evel during reset of phylink0/1 of 2.3. 1 ethernet signal 17 modification of l evel during reset of catsync1 of 2.3. 2 ethercat slave controller signal 18 addition of waitz1 - 3 port and list of note of 2.3.3 external memory interface signal 25 modification of l evel during reset of 2.3. 8 external interrupt input signal 26 modification of l evel during reset of tin 2/tout2 of 2.3. 8 external interrupt input signal and l evel during reset of 2.3. 10 watchdog timer output signal 30 modification of l evel during reset of 2.3.16 cc- link (remote device station) 31 addition the signal of vddq_pecl_b0/ vddq_pecl_b1 of 2 .3.17 system signal 34 modification of required connection when not in use of eth0_txc of 2.4.1 ethernet signal r - in32m3 series data sheet revision history c -2 rev. date description page summary preliminary 3.00 2013.1.17 36 modification of required connection when not in use of trstz of 2. 4.4 test signal 64 addition the figure of hw - rtos structure of 3.20 hardware real - time os 65 addition the list of service call of 3.20 hardware real - time os 1 .00 mar 29, 2013 overall modification of english expressions overall change the descripti on of ?cc - link ie field? ? cc - link ie field slave ? ? cc - link ie field (intelligent device station) ? overall change the description of ?cc - link? cc - link (slave) cc - link (remote device station) 1 modification of the contents of 1. 1 introduction 14 modification of the status of eth_mdc during the reset of 2.3.1 ethernet signals modif ication of the contents of note of 2.3.1 ethernet signals 18 modification of the status of busclk during the reset of 2.3.3 external memory interface signals 19 modification of the status of hd0 - hd15 during the reset of 2.3.4 external m pu interface signals 31 addition the signal s of hotresetz, vddq_mii, clkout25m0, clkout25m1 of 2.3.17 system signals modification of the function of ponrz of 2.3.17 syst em signals 53 modification of the status of the kind of supported station of 3.12 cc- link function 78 modification of the example calculation of 4.7.3 external memory interface signals (1) 78 modification of the min calculation result at the ti me of 30pf of 4.7.3 external memory interface signals (2) 81 modification of the min calculation result at the time of 30pf of 4.7.3 external memory interface signals (3) 84 addition the 4.7.4 external microcomputer interface signal 2.00 dec 9 ,2013 overall change the kind of cc - link station to support 3 standby mode deletion of table1.1 overview of r - in32m3 6 to 10 modification of the accessable area of ethercat of 1.5 memory map 28 addition explanation of function of 2.1.14 cc - link ie fiel d signals 31 modification of the function of vdd15 of 2.3.17 system signals addition the note to vddq_mii of 2.3.17 system signals 47 modification of wdt overflow time of 3.7 watchdog timer 71 addition of the value of supply current of 4.4 dc ch aracteristics 73 modification of the contents of 4.6 power - on/off sequence 80 modification of the contents of 4.7.3 external memory interface signals (3) 81 modification of the contents of figure 4.6 memory controller read timing diagram (synchro nous memory) 92 modification of thevalue of output delay time of ethn_txdm/ethn_txen, ethn_txer of 4.7.10 ethernet interface (1) r - in32m3 series data sheet revision history c -3 rev. date description page summary 2.01 feb 07 ,2014 6, 10 modification of the accessable area of ethercat of 1.5 memory map 30 add ccm_clk80m pins to list of 2.3.16 cc - link signal s (remote device station) 33 modification of boot mode select of 2.3.19 operation mode setting signals 37 addition the resister value for pull - up/down 39 modification of title name of 2.4.8 cc - link signal (intelligent device station, remote devic e station) 72 delete the description of 5k row of 4. 5 pull - up/down resister values 71 addition table4.6 dc characteristics typ value 86 addition the description at 4.7.5 serial flash rom interface 2.02 apr 18 ,2014 overall modification of cc - link signals (r emote device station) 39 modification of the description about ? r ecommended connection? and addition a caution description at 2.4.7 cc - link ie field signal 2.03 may 30 ,2014 73 add a notes of ? 4.6 power - on - off sequence ? 2 .04 dec 25 ,2014 3 change sta tus for intelligent device station for cc - link in 1.3 overview 6 to 10 modification of the accessible area of ethercat of 1.5 memory map 3 1 m odify the property for fb pin from ? - ? to ?input? 7 6 m odify the description of min value for low level wi dth in 4.7.2 reset signals 8 6 a dd description for ?asynchronous mode? in 4.7.4 external microcomputer interface signal . i nstruction s for the use of product in this section, the precautions are described for over whole of cmos device. please refer to this manual about individual precaution. when there is a mention unlike the text of this manual, a mention of the text takes first priority 1. handling of unused pins handle unused pins in accord with the directions given under handling of unused pins in the manual. - the input pins of cmos products are generally in the high- impedance state. in operation with an unused pin in the open- circuit state, extra electromagnetic noise is induced in the vicinity of lsi, associated shoot - through current flows interna lly, and malfunctions occur due to the false recognition of the pin state as an input signal become possible. unused pins should be handled as described under handling of unused pins in the manual. 2. processing at power -on the state of the product is undef ined at the moment when power is supplied. - the states of internal circuits in the lsi are indeterminate and the states of register settings and pins are undefined at the moment when power is supplied. in a finished product where the reset signal is applied to the external reset pin, the states of pins are not guaranteed from the moment when power is supplied until the reset process is completed. in a similar way, the states of pins in a product that is reset by an on - chip power - on reset function are not gua ranteed from the moment when power is supplied until the power reaches the level at which resetting has been specified. 3. prohibition of access to reserved addresses access to reserved addresses is prohibited. - the reserved addresses are provided for the pos sible future expansion of functions. do not access these addresses; the correct operation of lsi is not guaranteed if they are accessed. 4. clock signals after applying a reset, only release the reset line after the operating clock signal has become stable. when switching the clock signal during program execution, wait until the target clock signal has stabilized. - when the clock signal is generated with an external resonator (or from an external oscillator) during a reset, ensure that the reset line is only r eleased after full stabilization of the clock signal. moreover, when switching to a clock signal produced with an external resonator (or by an external oscillator) while program execution is in progress, wait until the target clock signal is stable. ? arm, amba, arm cortex, thumb and arm cortex - m3 are a trademark or a registered trademark of arm limited in eu and other countries. ? ethernet is a registered trademark of fuji zerox limited. ? ieee is a registered trademark of the institute of electrical and electronics engineers, inc. ? ethercat is a registered trademark of beckhoff automation gmbh, germany . ?cc- link and cc - link ie field are a registered trademark of cc- link partner association ( clpa ). ? additionally all product names and service names in this document are a trademark or a registered trademark whic h belongs to the respective owners. ? real - time os accelerator and hardware real - time os is based on hardware real - time os of ?artesso? made in kernelon silicon inc. renesas electronics america inc. 2880 scott boulevard santa clara, ca 95050 - 2554, u.s.a. tel: +1 - 408 - 588 - 6000, fax: +1 - 408- 588 - 6130 renesas electronics canada limited 1101 nicholson road, newmarket, ontario l3y 9c3, canada tel: +1 - 905 - 898 - 5441, fax: +1 - 905- 898 - 3220 renesas electronics europe limited dukes meadow, millboard road, bourne end, buckinghamshire, sl8 5fh, u.k tel: +44 - 1628 - 651- 700, fax: +44 - 1628 - 651 - 804 renesas electronics europe gmbh arca diastrasse 10, 40472 dsseldorf, germany tel: +49 - 211 - 65030, fax: +49 - 211 - 6503 - 1327 renesas electronics (china) co., ltd. 7th floor, quantum plaza, no.27 zhichunlu haidian district, beijing 100083, p.r.china tel: +86 - 10 - 8235 - 1155, fax: +86 - 10- 8235- 7679 ren esas electronics (shanghai) co., ltd. unit 204, 205, azia center, no.1233 lujiazui ring rd., pudong district, shanghai 200120, china tel: +86 - 21 - 5877 - 1818, fax: +86 - 21- 6887- 7858 / - 7898 renesas electronics hong kong limited unit 1601 - 1613, 16/f., tower 2, grand century place, 193 prince edward road west, mongkok, kowloon, hong kong tel: +852 - 2886 - 9318, fax: +852 2886 - 9022/9044 renesas electronics taiwan co., ltd. 13f, no. 363, fu shing north road, taipei, taiwan tel: +886 - 2 - 8175 - 9600, fax: +886 2 - 8175 - 9670 renesas electronics singapore pte. ltd. 80 bendemeer road, unit #06 - 02 hyflux innovation centre singapore 339949 tel: +65 - 6213 - 0200, fax: +65 - 6213 - 0300 renesas electronics malaysia sdn.bhd. unit 906, block b, menara amcorp, amcorp trade centre, no. 18, jln persiaran barat, 46050 petaling jaya, selangor darul ehsan, malaysia tel: +60 - 3 - 7955 - 9390, fax: +60 - 3 - 7955 - 9510 renesas electronics korea co., ltd. 11f., samik lavied' or bldg., 720 - 2 yeoksam - dong, kangnam - ku, seoul 135 - 080, korea tel: +82 - 2 - 558 - 3737, fax : +82 - 2 - 558 - 5141 ? 2012 - 2014 renesas electronics corporation. all rights reserved notice 1. descriptions of circuits, software and other related information in this docume nt are provided only to illustrate the operation of semiconductor products and application examples. you are fully responsible for the incorporation of these circuits, software, and information in the design of your equipment. renesas electronics assumes n o responsibility for any losses incurred by you or third parties arising from the use of these circuits, software, or information. 2. renesas electronics has used reasonable care in preparing the information included in this document, but renesas electron ics does not warrant that such information is error free. renesas electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information in cluded herein. 3. renesas electronics does not assu me any liability for infringement of patents, copyrights, or other intellectual property rights of third parties by or arisin g from the use of renesas electronics products or technical information described in this document. no license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights of renesas electronics or others. 4. you should not alter, modify, copy, or otherwise misappropriate any renesas electronics product, whether in whole or in part. renesas electronics assumes no responsibility for any losses incurred by you or third parties arising from such alteration, modification, copy or otherwise misappropriation of renesas electronics product. 5. renesas electronics products are classifi ed according to the following two quality grades: "standard" and "high quality". the recommended applications for each renesa s electronics product depends on the product's quality grade, as indicated below. "standard": computers; office equipment; comm unications equipment; test and measurement equipment; audio and visual equipment; home electronic appliances; machine tools; personal electronic equipment; and industrial robots etc. "high quality": transportation equipment (automobiles, trains, ships, et c.); traffic control systems; anti - disaster systems; anti - crime systems; and safety equipment etc. renesas electronics products are neither intended nor authorized for use in products or systems that may pose a direct threat to human life or bodily injury (artificial life support devices or systems, surgical implantations etc.), or may cause serious property damages (nuclear reactor control systems, military equipment etc.). you must check the quality grade of each renesas electronics product before using it in a particular application. you may not use any renesas electronics product for any application for which it is not intended. renesas electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any renesas electronics product for which the product is not intended by renesas electronics. 6. you should use the renesas electronics products described in this document within the range specified by renesas electronics, especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. renesas electronics shall have no liability for malfunctions or damages arising out of the use of renesas electronics products beyond such specified ranges. 7. although renesas electronics endeavors to improve the quality and reliability of its products, semiconductor products have sp ecific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. further, renesas electronics products are not subject to radiation resistance desi gn. please be sure to implement safety measures to guard them against the possibility of physical injury, and inj ury or damage caused by fire in the event of the failure of a renesas electronics product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging deg radation or any other appropriate measures. because the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or systems manufactured by you. 8. please contact a renesas electronics sales office for details as to environmental matters such as the environmental compatibility of each renesas electronics product. please use renesas electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlle d substances, including without limitation, the eu rohs directive. renesas electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations. 9. renesas electronics products and technol ogy may not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. you should not use renesas electronics products or technology described in this document for any purpose relating to military applications or use by the military, including but not limited to the development of weapons of mass destruction. when exporting the renesas electronics products or technology described in this d ocument, you s hould comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations. 10. it is the responsibility of the buyer or distributor of renesas electronics products, who distributes, disposes of, or otherwise places the product with a third party, to notify such third party in advance of the contents and conditions set forth in this document, renesas electronics assumes no responsibility for any losses incurred by you or third parties as a result of unauthorized use of renesas electronics products. 11. this document may not be reproduced or duplicated in any form, in whole or in part, without prior written consent of rene sas electronics. 12. please contact a renesas electronics sales office if you hav e any questions regarding the information contained in this document or renesas electronics products, or if you have any othe r inquiries. (note 1) "renesas electronics" as used in this document means renesas electronics corporation and also includes its m ajority - owned subsidiaries. (note 2) "renesas electronics product(s)" means any product developed or manufactured by or for renesas electronics. |
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